What a weird instruction.

llvm-svn: 114190

llvm-svn: 114183

llvm-svn: 114173

llvm-svn: 114116

(PICLDRB, et. al.) and PICSTR*

llvm-svn: 114098

from the APFloat.

llvm-svn: 114096

This cleans up after the mess r108567 left in the CellSPU backend.
ORCvt-instruction were used to reinterpret registers, and the ORs were then
removed by isMoveInstr(). This patch now removes 350 instrucions of format:
	or $3, $3, $3
(from the 52 testcases in CodeGen/CellSPU). One case of a nonexistant or is
checked for.

Some moves of the form 'ori $., $., 0' and 'ai $., $., 0' still remain.

llvm-svn: 114074

used for anything.

llvm-svn: 114067

instead of using default predicates on the expanded instructions.

llvm-svn: 114066

unnecessary dtor for MCOperand.

llvm-svn: 114064

llvm-svn: 114048

register allocation to VLDMD and VSTMD respectively.  This avoids using the
dregpair operand modifier.

llvm-svn: 114047

llvm-svn: 114030

llvm-svn: 114026

llvm-svn: 114025

moves. Previously, the immediate was printed as the encoded integer value,
which is incorrect.

llvm-svn: 114021

functions in ARMBaseInfo.h so it can be used in the MC library as well.
For anything bigger than this, we may want a means to have a small support
library for shared helper functions like this. Cross that bridge when we
come to it.

llvm-svn: 114016

merge the common cases.

llvm-svn: 114013

if the register is a member of the SPR register class directly instead.

llvm-svn: 114012

llvm-svn: 114009

llvm-svn: 114008

between the compiler back end and the MC libraries.

llvm-svn: 114007

VFP instructions use it for loading some constants, so implement that
handling.

Not thrilled with adding a member to MCOperand, but not sure there's much of
a better option that's not pretty fragile (like putting a double in the
union instead and just assuming that's good enough). Suggestions welcome...

llvm-svn: 113996

Recognize VLD1q64Pseudo as a stack slot load.

Reject these if they are loading or storing a subregister. The API (and
VirtRegRewriter) doesn't know how to deal with that.

llvm-svn: 113985

encountered while building llvm-gcc for arm.  This is probably the same issue
that the ppc buildbot hit. llvm::prior works on a MachineBasicBlock::iterator,
not a plain MachineInstr.

llvm-svn: 113983

backing out following to get it back to green,
so I can investigate in peace:

svn merge -c -113840  llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll
svn merge -c -113876 -c -113839 llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

llvm-svn: 113980

forgotten in the future.

Coalesce identical cases in switch.

No functional changes intended.

llvm-svn: 113979

llvm-svn: 113978

wraps up r8418316

llvm-svn: 113949

for call.  Add this.

llvm-svn: 113948

even in 64-bit mode apparently.

llvm-svn: 113945

add sldt GR32, which isn't documented in the intel manual
but which gas accepts.  Part of rdar://8418316

llvm-svn: 113938

llvm-svn: 113937

llvm-svn: 113936

version because it adds a prefix and makes even less sense
than the other broken forms.  This wraps up rdar://8431422

llvm-svn: 113932

llvm-svn: 113930

rdar://8431422

llvm-svn: 113929

instead of crashing.  This fixes:
rdar://8431815 - crash when invalid operand is one that isn't present

llvm-svn: 113921

storeRegToStackSlot.

llvm-svn: 113918

llvm-svn: 113915