(I discovered 2 more copies of the ARM instruction format list, bringing the
total to 4!!  Two of them were already out of sync.  I haven't yet gotten into
the disassembler enough to know the best way to fix this, but something needs
to be done.)  Add support for encoding these instructions.

llvm-svn: 110754

llvm-svn: 110363

Partial fix for PR7792.

llvm-svn: 110361

Partial fix for PR7792.

llvm-svn: 110358

the jtblock_operand print methods.  This avoids extra newlines in the
disassembler's output.  PR7757.

llvm-svn: 109948

llvm-svn: 109813

Add intrinsics __builtin_arm_qadd & __builtin_arm_qsub to allow access to the QADD & QSUB instructions.
Behave identically to __qadd & __qsub RealView instruction intrinsics.

llvm-svn: 109770

ARM mode version of r109693. Remove incorrect substitution pattern for UXTB16. It wrongly assumed the input shift was actually a rotate. rdar://8240138

llvm-svn: 109696

and a combine pattern to use it for setting a bit-field to a constant
value. More to come for non-constant stores.

llvm-svn: 108570

in the literal field of an instruction. E.g.,
long long foo(long long a) {
  return a - 734439407618LL;
}

rdar://7038284

llvm-svn: 108339

Extend the r107852 optimization which turns some fp compare to code sequence using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0.

llvm-svn: 108258

Add explicit testcases for tail calls within the same module.
Duplicate some code to humor those who think .w doesn't apply on ARM.
Leave this disabled on Thumb1, and add some comments explaining why it's hard
and won't gain much.

llvm-svn: 107851

being moved around away from the jump table it references. rdar://8104340

llvm-svn: 106483

handling, plus correct R9 handling in that mode.

llvm-svn: 106434

llvm-svn: 106362

llvm-svn: 106314

ARM tail calls.  Don't know if it works, but it
doesn't break Darwin.

llvm-svn: 106309

Not turning them on yet.

llvm-svn: 106295

llvm-svn: 106058

A temporary flag -arm-tail-calls defaults to off,
so there is no functional change by default.
Intrepid users may try this; simple cases work
but there are bugs.

llvm-svn: 105413

llvm-svn: 105350

llvm-svn: 104980

make sure accesses to set up the jmpbuf don't get moved after it by the scheduler. Add a missing \n.

llvm-svn: 104967

an alloca() or an llvm.stackrestore(). rdar://8031573

llvm-svn: 104900

ISD::. No functional change.

llvm-svn: 104734

Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.

llvm-svn: 104419

llvm-svn: 104114

Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects.

llvm-svn: 104111

Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM.

llvm-svn: 104102

llvm-svn: 103903

Temporary emit it as raw bytes until it will be added to binutils as well.

llvm-svn: 103878

llvm-svn: 103459

instructions to subtarget features and update tests to reflect.
PR5717.

llvm-svn: 103136

Jordy <snhjordy@gmail.com>.

Followup patches will add some tests and adjust to use Subtarget features
for the instructions.

llvm-svn: 103119

to the UAL syntax of LDCL<c>, instead.

Add a test case for this change which also tests the removal of assert() from
printAddrMode2OffsetOperand().

llvm-svn: 101527

am2offset.  Modified the instruction table entry and added a new test case.

llvm-svn: 101415

such that the non-VFP versions have no implicit defs of VFP registers.
If any callee-saved VFP registers are marked as having been defined, the
prologue/epilogue code will try to save and restore them.
Radar 7770432.

llvm-svn: 100892

Preliminary testing shows significant performance wins by not using these
instructions.

llvm-svn: 99436

with changes to add a separate optional register update argument.  Change all
the NEON instructions with address register writeback to use it.

llvm-svn: 99095

IndexModeUpd and then populates the Inst{21}=1 while populating the instructions
for disassembly.

llvm-svn: 99013