- This manifested as non-determinism in the .inc output in rare cases (when two
   distinct patterns ended up being equivalent, which is rather rare). That
   meant the pattern matching was non-deterministic, which could eventually mean
   the code generator selected different instructions based on the arch.

 - It's probably worth making the DAGISel ensure a total ordering (or force the
   user to), but the simple fix here is to totally order the Record* maps based
   on a unique ID.

 - PR4672, PR4711.

Yay:
--
ddunbar@giles:~$ cat ~/llvm.obj.64/lib/Target/*/*.inc | shasum
d1099ff34b21459a5a3e7021c225c080e6017ece  -
ddunbar@giles:~$ cat ~/llvm.obj.ppc/lib/Target/*/*.inc | shasum
d1099ff34b21459a5a3e7021c225c080e6017ece  -
--

llvm-svn: 79846

update all code that this affects.

llvm-svn: 79830

llvm-svn: 79821

instead of as two bools.  Use this to add a F_Append flag
which has the obvious behavior.

Other unrelated changes conflated into this patch:

1. REmove EH stuff from llvm-dis and llvm-as, the try blocks
   are dead.
2. Simplify the filename inference code in llvm-as/llvm-dis,
   because raw_fd_ostream does the right thing with '-'.
3. Switch machine verifier to use raw_ostream instead of ostream
   (Which is the thing that needed append in the first place).

llvm-svn: 79807

llvm-svn: 79742

Extend the instruction itinerary model to include the ability to indicate the def and use cycle for each operand. This additional information is optional, so existing itineraries do not need to be changed.

llvm-svn: 79247

just remove the argument and replace it with 1.

llvm-svn: 79246

llvm-svn: 78948

There have been a few times where I've wanted this but ended up leaving the
operand type unconstrained.  It is easy to add this now and should help
catch errors in the future.

llvm-svn: 78849

llvm-svn: 78848

Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one.

llvm-svn: 78827

Add contexts to some of the MVT APIs.  No functionality change yet, just the infrastructure work needed to get the contexts to where they need to be first.

llvm-svn: 78759

We now match all of 403.gcc (as emitted by clang). :)

llvm-svn: 78750

 - Used to mark fake instructions which don't correspond to an actual machine
   instruction (or are duplicates of a real instruction). This is to be used for
   "special cases" in the .td files, which should be ignored by things like the
   assembler and disassembler. We still need a good solution to handle pervasive
   duplication, like with the Int_ instructions.

 - Set the bit on fake "mov 0" style instructions, which allows turning an
   assembler matcher warning into a hard error.

 - -2 FIXMEs.

llvm-svn: 78731

used to strip hard coded comments out of .td assembly strings.

llvm-svn: 78716

the latter is capable of representing either a primitive or an extended type.

llvm-svn: 78713

related.

llvm-svn: 78706

llvm-svn: 78643

 - This drops us to 123 ambiguous instructions (previously ~500) on X86.

llvm-svn: 78636

arguments that are vectors of any size and element type.

llvm-svn: 78631

llvm-svn: 78610

on target specific operands for testing class membership and converting to
MCInst operands.

llvm-svn: 78597

explicit parser match classes.

llvm-svn: 78588

structure.

llvm-svn: 78581

instruction operands.

llvm-svn: 78565

llvm-svn: 78533

make it easier to see interesting ambiguities.
 - Also, check that user doesn't try to redefine the super class. This is a wart
   in the current design, in that assembler match classes aren't explicitly
   declared somewhere (so there isn't a unique place to declare the super
   class). This should probably be fixed.

llvm-svn: 78532

 - We can now discriminate SUB32ri8 from SUB32ri, for example.

llvm-svn: 78530

 - We want the ordering operation to be simple, since we run it on every
   match. The old ordering is also not a strict weak ordering when there are
   ambiguities, which makes MSVC unhappy.

 - While we are at it, detect all ambiguities instead of just the adjacent
   ones. There are actually 655, for X86.

llvm-svn: 78526

 -2 FIXMEs.

llvm-svn: 78523

ambiguities.
 - Currently there are 483 ambiguities to resolve. :)

llvm-svn: 78522

llvm-svn: 78520

llvm-svn: 78518

 - Track whether we need to insert an explicit 'break'.

 - Invert conditional when matching a single prefix to reduce
   nesting/bracing/breaking.

 - wc -l of X86GenAsmMatcher.inc decreased by 10%. :)

llvm-svn: 78513

Also, redefined MatchRegisterName to just return the register value or a
sentinel, to simplify the generated code.

llvm-svn: 78504

much more efficient way than a sequence of if's.  Switch MatchRegisterName
to use it.  It would be nice if someone could factor this out to a shared
place in tblgen :)

llvm-svn: 78492

llvm-svn: 78487

llvm-svn: 78486

llvm-svn: 78462

 - This doesn't actually improve the algorithm (its still linear), but the
   generated (match) code is now fairly compact and table driven. Still need a
   generic string matcher.

 - The table still needs to be compressed, this is quite simple to do and should
   shrink it to under 16k.

 - This also simplifies and restructures the code to make the match classes more
   explicit, in anticipation of resolving ambiguities.

llvm-svn: 78461