llvm-svn: 4811

llvm-svn: 4810

llvm-svn: 4809

llvm-svn: 4808

llvm-svn: 4807

llvm-svn: 4806

llvm-svn: 4805

llvm-svn: 4804

llvm-svn: 4803

llvm-svn: 4802

pass.  Detect and flag them.

llvm-svn: 4801

register versions

llvm-svn: 4800

llvm-svn: 4799

llvm-svn: 4798

llvm-svn: 4797

llvm-svn: 4796

Basically just adds OpSize flags for instructions that need them.

llvm-svn: 4795

llvm-svn: 4794

for example.

llvm-svn: 4793

doesn't assert fail. And everyone's happy. Yay!

llvm-svn: 4792

llvm-svn: 4791

llvm-svn: 4790

llvm-svn: 4789

llvm-svn: 4788

llvm-svn: 4787

llvm-svn: 4786

llvm-svn: 4785

Some functions are in X86RegisterInfo.cpp, others, because of the data they
need, are in X86RegisterClasses.cpp, which also defines some register classes:
byte, short, and int.

llvm-svn: 4784

printing out assembly. After all, we want the real thing too.

llvm-svn: 4783

llvm-svn: 4782

an appropriate TargetRegisterClass, also adds TargetRegisterClass definition.
TargetMachine.h - speling.

llvm-svn: 4781

llvm-svn: 4780

    wasn't an optimization and it was causing lots of bugs.

llvm-svn: 4779

llvm-svn: 4778

and it causes obscure bugs to show up in passes.

llvm-svn: 4777

uncovered a bug where registers were not being put in a map if they were not
found...

llvm-svn: 4776

llvm-svn: 4775

imply types of SSA Registers. This is on a per-function basis, so the
MachineFunction contains the SSARegMap, and has accessor functions to it.

llvm-svn: 4774

belong to different register classes easier.

llvm-svn: 4773

llvm-svn: 4772