pool entry will require relocations against it.  I implemented this
conservatively for ARM, someone who is knowledgable about it should
see if this can be improved.

llvm-svn: 76678

getAnalysisIfAvailable<TargetData>.

llvm-svn: 76676

to help support use when TargetData is not available.

llvm-svn: 76675

their appropriate sections before the code itself. They need to be emitted
before the function because on some targets (x86 but not x86_64) the later
may reference a JT or CP entry address

llvm-svn: 76672

(x pred y) with more thorough code that does more complete canonicalization
before resorting to range checks. This helps it find more cases where
the canonicalized expressions match.

llvm-svn: 76671

depends on XS1A, but I think the ReadOnlySection is already set up for this
and there is no testcase that this breaks.  If this is really needed, we can
add the appropriate parameterization to TargetAsmInfo in the future to support
this.

llvm-svn: 76667

llvm-svn: 76666

if Xcore doesn't support TLS, it doesn't have to worry about thread local LLVM IR, it should be rejected by a front-end.

llvm-svn: 76665

to twist your brain to see it, I believe it is the same as ELFTargetAsmInfo::SelectSectionForGlobal.

llvm-svn: 76664

llvm-svn: 76662

llvm-svn: 76661

the generic ELF version instead.  This will result in its mergable constant
sections getting named ".rodata.cst4" instead of ".cp.const4", but the
linker looks at the section flags, not the name of the section AFAICT.

llvm-svn: 76659

llvm-svn: 76654

implemented exactly the same way as its ELFTargetAsmInfo subclass 
has them.

llvm-svn: 76653

llvm-svn: 76646

llvm-svn: 76645

llvm-svn: 76639

llvm-svn: 76635

llvm-svn: 76634

be useful, and it's currently unused.  (Some issues: it isn't actually 
rich enough to capture the semantics on many architectures, and
semantics can vary depending on the type being shifted.)

llvm-svn: 76633

llvm-svn: 76631

Prefix IR dumps with LiveInterval indices when possible.  This turns
this:

	%ESI<def> = MOV32rr %EDI<kill>
	ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
	%reg1027<def> = MOVZX64rr32 %ESI
	%reg1027<def> = ADD64ri8 %reg1027, 15, %EFLAGS<imp-def,dead>
	%reg1027<def> = AND64ri8 %reg1027, -16, %EFLAGS<imp-def,dead>
	%RDI<def> = MOV64rr %RSP
	%RDI<def> = SUB64rr %RDI, %reg1027<kill>, %EFLAGS<imp-def,dead>
	%RSP<def> = MOV64rr %RDI

into this:

4	%reg1024<def> = MOV32rr %EDI<kill>
12	ADJCALLSTACKDOWN64 0, %RSP<imp-def>, %EFLAGS<imp-def,dead>, %RSP<imp-use>
20	%reg1025<def> = MOVZX64rr32 %reg1024
28	%reg1026<def> = MOV64rr %reg1025<kill>
36	%reg1026<def> = ADD64ri8 %reg1026, 15, %EFLAGS<imp-def,dead>
44	%reg1027<def> = MOV64rr %reg1026<kill>
52	%reg1027<def> = AND64ri8 %reg1027, -16, %EFLAGS<imp-def,dead>
60	%reg1028<def> = MOV64rr %RSP
68	%reg1029<def> = MOV64rr %reg1028<kill>
76	%reg1029<def> = SUB64rr %reg1029, %reg1027<kill>, %EFLAGS<imp-def,dead>
84	%RSP<def> = MOV64rr %reg1029

This helps greatly when debugging register allocation and coalescing
problems.

llvm-svn: 76615

llvm-svn: 76612

and call PrintGlobalVariable, allowing elimination and simplification
of various targets.

llvm-svn: 76604

Add PrefixPrinter arguments to the dump routines for MachineFunction and
MachineBasicBlock.  We'll use these shortly.

llvm-svn: 76603

llvm-svn: 76600

llvm-svn: 76598

llvm-svn: 76596

llvm-svn: 76595

chain to the super class instead of initializing mangler directly.
This gives it .file and module level inline asm support among other
things.

llvm-svn: 76593

This eliminates redundancy setting up the mangler and adds support to them
for module-level inline asm and a .file directive.

llvm-svn: 76592

LLVM IR concept.

llvm-svn: 76590

llvm-svn: 76587

llvm-svn: 76586

vectors needlessly, doxygenify comments, improve constness, etc.

llvm-svn: 76585

as much, etc.

llvm-svn: 76578

Another rewriter bug exposed by recent coalescer changes. ReuseInfo::GetRegForReload() should make sure the "switched" register is in the desired register class. I'm surprised this hasn't caused more failures in the past.

llvm-svn: 76558

llvm-svn: 76555

llvm-svn: 76554

llvm-svn: 76553