llvm-svn: 55259

llvm-svn: 55258

llvm-svn: 55257

llvm-svn: 55252

up to three values in one call.

llvm-svn: 55251

according to the intarnetz

llvm-svn: 55248

all the power and risk of fprintf format strings.  Use them like this:

  OS << format("%10.4f", 42.0) << "\n" << format("%x", 42) << '\n';

llvm-svn: 55246

llvm-svn: 55239

Is there way to avoid explicit target check?

llvm-svn: 55238

tests:

Running /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.HEAD.src/test/Verifier/dg.exp ...
FAIL: /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.HEAD.src/test/Verifier/gcread-ptrptr.ll for PR1633
Failed with exit(1) at line 1
while running: not llvm-as < /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.HEAD.src/test/Verifier/gcread-ptrptr.ll >& /dev/null
child process exited abnormally
FAIL: /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.HEAD.src/test/Verifier/gcroot-alloca.ll for PR1633
Failed with exit(1) at line 1
while running: not llvm-as < /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.HEAD.src/test/Verifier/gcroot-alloca.ll >& /dev/null
child process exited abnormally
FAIL: /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.HEAD.src/test/Verifier/gcroot-meta.ll for PR1633
Failed with exit(1) at line 1
while running: not llvm-as < /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.HEAD.src/test/Verifier/gcroot-meta.ll >& /dev/null
child process exited abnormally
FAIL: ndbox/Buildbot/llvm/full-llvm/build/llvm.HEAD.src/test/Verifier/gcroot-ptrptr.ll for PR1633
Failed with exit(1) at line 1
while running: not llvm-as < /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.HEAD.src/test/Verifier/gcroot-ptrptr.ll >& /dev/null
child process exited abnormally
FAIL: /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.HEAD.src/test/Verifier/gcwrite-ptrptr.ll for PR1633
Failed with exit(1) at line 1
while running: not llvm-as < /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.HEAD.src/test/Verifier/gcwrite-ptrptr.ll >& /dev/null
child process exited abnormally

		===  Summary ===

# of expected passes		3021
# of unexpected failures	6
# of expected failures		16
make[1]: *** [check-local] Error 1
make: *** [check] Error 2

llvm-svn: 55233

before/after effects of a pass, crazy!

llvm-svn: 55230

integer, PR2318.

llvm-svn: 55228

and tblgen now knows intrinsic prototypes.

llvm-svn: 55227

indices that start with an array subscript.  x->field[10000] is just 
as bad as (*X)[14][10000].

llvm-svn: 55226

llvm-svn: 55224

llvm-svn: 55220

process up to a higher level. This allows FastISel to leverage
more of SelectionDAGISel's infastructure, such as updating Machine
PHI nodes.

Also, implement transitioning from SDISel back to FastISel in
the middle of a block, so it's now possible to go back and
forth. This allows FastISel to hand individual CallInsts and other
complicated things off to SDISel to handle, while handling the rest
of the block itself.

To help support this, reorganize the SelectionDAG class so that it
is allocated once and reused throughout a function, instead of
being completely reallocated for each block.

llvm-svn: 55219

i8* getelementptr. DAGCombine eliminates these, but this is
a fairly common case.

llvm-svn: 55214

llvm-svn: 55212

llvm-svn: 55210

These just test that they go through the BE.

llvm-svn: 55208

llvm-svn: 55206

llvm-svn: 55205

llvm-svn: 55203

{standard input}:17:bad register name `%sil'
make[4]: *** [libgcc/./_addvsi3.o] Error 1
make[4]: *** Waiting for unfinished jobs....
{standard input}:23:bad register name `%dil'
{standard input}:28:bad register name `%dil'
make[4]: *** [libgcc/./_addvdi3.o] Error 1
{standard input}:18:bad register name `%sil'
make[4]: *** [libgcc/./_subvsi3.o] Error 1

llvm-svn: 55200

llvm-svn: 55192

llvm-svn: 55191

instructions that define the full 32 or 64-bit value. When anyexting
from i8 to i16 or i32, it's not necessary to zero out the high
portion of the register.

llvm-svn: 55190

llvm-svn: 55189

are not yet updated properly, but that's a separate
task.

llvm-svn: 55187

llvm-svn: 55186

llvm-svn: 55182

handled correctly, and change a few SmallVector uses to use
size 0 to more clearly reflect their intent.

llvm-svn: 55181

Patch contributed by Bjorn Reese!

llvm-svn: 55179

llvm-svn: 55173

llvm-svn: 55171

Patch contributed by m-s.

llvm-svn: 55167

so that lwarx and stwcx are always executed the same number of times.
This is important for performance, I'm told.

llvm-svn: 55163

llvm-svn: 55157

and use it in FastISelEmitter.cpp, and make FastISel
subtarget aware. Among other things, this lets it work
properly on x86 targets that don't have SSE, where it
successfully selects x87 instructions.

llvm-svn: 55156