llvm-svn: 140955

Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702.

llvm-svn: 140954

This is the first step towards splitting LLVM and Clang's tblgen executables.

llvm-svn: 140951

llvm-svn: 140928

All the sub-class bit vectors are computed when first creating the
register bank.

llvm-svn: 140905

This uses less memory and it reduces the complexity of sub-class
operations:

- hasSubClassEq() and friends become O(1) instead of O(N).

- getCommonSubClass() becomes O(N) instead of O(N^2).

In the future, TableGen will infer register classes.  This makes it
cheap to add them.

llvm-svn: 140898

This one can also print 32-bit groups.

llvm-svn: 140897

Use these lists instead of computing them on the fly in
RegisterInfoEmitter.

llvm-svn: 140895

Implement VarListElementInit:: resolveListElementReference so that
lists of lists can be indexed.

llvm-svn: 140882

llvm-svn: 140827

All register classes are given a lower ID than their sub-classes.
Cliques are ordered alphabetically.

This will be used to simplify some sub-class operations.

llvm-svn: 140826

This makes it possible to allocate CodeGenRegisterClass instances
dynamically and reorder them.

llvm-svn: 140816

"show-in-system-header" bits, which I will be adding in Clang shortly.

llvm-svn: 140741

llvm-svn: 140573

llvm-svn: 140560

Many targets use pseudo instructions to help register allocation.  Like
the COPY instruction, these pseudos can be expanded after register
allocation.  The early expansion can make life easier for PEI and the
post-ra scheduler.

This patch adds a hook that is called for all remaining pseudo
instructions from the ExpandPostRAPseudos pass.

llvm-svn: 140472

llvm-svn: 140370

No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.

llvm-svn: 140160

Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile

llvm-svn: 140134

llvm-svn: 140121

llvm-svn: 140078

Report missing template arguments more helpfully by supplying the name
of the missing argument in the error message.

llvm-svn: 140034

llvm-svn: 139936

this anymore.

llvm-svn: 139935

Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND from being recognized by disassembler.

llvm-svn: 139691

llvm-svn: 139617

llvm-svn: 139598

Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848.

llvm-svn: 139588

llvm-svn: 139485

Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W.

llvm-svn: 139484

llvm-svn: 139414

llvm-svn: 139381

llvm-svn: 139317

This patch was written by DeLesley Hutchins.

llvm-svn: 139300

llvm-svn: 139286

Speculatively try to fix our windows testers with a patch I found on the internet.

llvm-svn: 139279

llvm-svn: 139278

llvm-svn: 139267

The immediate offset of the non-writeback i8 form (encoding T4) allows
negative offsets only. The positive offset form of the encoding is the
LDRT instruction. Immediate offsets in the range [0,255] use encoding T3
instead.

llvm-svn: 139254

Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler.

llvm-svn: 139250