use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.

Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'm not 100% sure if it's necessary to change it there...

llvm-svn: 70270

llvm-svn: 70262

llvm-svn: 70247

llvm-svn: 70245

between the comparison's iv stride and the candidate stride is
exactly -1.

llvm-svn: 70244

information to simplify [sz]ext({a,+,b}) to {zext(a),+,[zs]ext(b)},
as appropriate.

These functions and the trip count code each call into the other, so
this requires careful handling to avoid infinite recursion. During
the initial trip count computation, conservative SCEVs are used,
which are subsequently discarded once the trip count is actually
known.

Among other benefits, this change lets LSR automatically eliminate
some unnecessary zext-inreg and sext-inreg operation where the
operand is an induction variable.

llvm-svn: 70241

This should have no effect on generated code, but makes the intermediate state
of the coalescer more sane.

llvm-svn: 70238

no-longer needed workarounds.

llvm-svn: 70234

PR2957

ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask.  A value of -1 represents UNDEF.

In addition to eliminating the creation of illegal BUILD_VECTORS just to 
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.

llvm-svn: 70225

Fix PR4056. It's possible a physical register def is dead if its implicit use is deleted by two-address pass.

llvm-svn: 70213

llvm-svn: 70212

to precisely describe the h-register subreg register classes.
Thanks to Jakob Stoklund Olesen for spotting this and for the
initial patch!

Also, make getStoreRegOpcode and getLoadRegOpcode aware of the
needs of h registers.

llvm-svn: 70211

GR32_ABCD, and GR64_ABCD, respectively, to help describe them.

llvm-svn: 70210

llvm-svn: 70209

llvm-svn: 70197

another stub, but then never calling the jitted function) can cause the JIT to
leave a stub in place. Judging by the comments this is a known deficiency, so
we're just not going to use AssertingVH for the StubToFunctionTy map.

Also shorten some lines longer than 80 columns.

This fixes the "make check" failure with ocaml on x86-64 linux.

llvm-svn: 70185

the trunc is directly replaced with the smaller load, so don't
try to create a new sext node. This fixes PR4050.

llvm-svn: 70179

llvm-svn: 70176

state out of the BitstreamReader class into a BitstreamCursor class.
Doing this allows the client to have multiple cursors into the same
file, each with potentially different live block stacks and
abbreviation records.

llvm-svn: 70157

Any size of integral indices are allowed in gep for indexing into sequential types. Also adding a test case to check the indices type allowed into struct.

llvm-svn: 70134

llvm-svn: 70080

The real fix for this whole mess is to require the operand of the
alias to be a *GlobalValue* (not a general constant, including 
constant exprs) but allow the operand and the alias type to be
unrelated.

This fixes PR4066

llvm-svn: 70079

llvm-svn: 70069

patch by Jeff Yasskin!

llvm-svn: 70058

Nicolas Capens!

llvm-svn: 70057

using EXTRACT_ELEMENT into a utility function.

llvm-svn: 70056

llvm-svn: 70054

into unsigned ones when the operands are known to have the same
sign bit value.

llvm-svn: 70053

llvm-svn: 70052

common, but indvars shouldn't crash on them. This fixes PR4054.

llvm-svn: 70051

Path.cpp:59: warning: case label value exceeds maximum value for type
magic[0] is a (signed) char, but some case values are unsigned (e.g. 0xde).
When magic[0] was 0xde, the switch has taken the default branch instead of case
0xde branch.
Apparently this was the behaviour with older versions of gcc too, but not with g++.
Now g++-4.4 behaves as gcc, and ignores unsigned case values out of range signed
range.

llvm-svn: 70038

Do not share a single unknown val# for all the live ranges merged into a physical sub-register live interval. When coalescer is merging in clobbered virtaul register live interval into a physical register live interval, give each virtual register val# a separate val# in the physical register live interval. Otherwise, the coalescer would have lost track of the definitions   information it needs to make correct coalescing decisions.

llvm-svn: 70026

f64 types.  This is not used for anything yet.

llvm-svn: 70006

This particular one is undefined behavior (although this
isn't related to the crash), so it will no longer do it
at compile time, which seems better.

llvm-svn: 69990

between registers and the stack may be required with the APCS ABI, but it
isn't tied to using a particular version of the ARM architecture.

llvm-svn: 69978

chained and "flagged" together.  I also made a few changes to handle the
chain and flag values more consistently.  I found these problems by
inspection so I'm not aware of anything that breaks because of them
(thus no testcase).

llvm-svn: 69977

should be bit-converted to i32, it is sufficient to list only i32 in
subsequent definitions.

llvm-svn: 69973

very elegant, but neither is the tls specification :-(

llvm-svn: 69968

llvm-svn: 69967

ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask.  A value of -1 represents UNDEF.

In addition to eliminating the creation of illegal BUILD_VECTORS just to 
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.

A clean up of x86 shuffle code, and some canonicalizing in DAGCombiner is next.

llvm-svn: 69952