because the boolean it returns to indicate an overflow may not be treated like
as a flag. It could be stored to memory, for instance.

llvm-svn: 59780

"ISD::ADDO". ISD::ADDO is lowered into a target-independent form that does the
addition and then checks if the result is less than one of the operands. (If it
is, then there was an overflow.)

llvm-svn: 59779

llvm-svn: 59777

schedulers. This doesn't have much immediate impact because
targets that use these schedulers by default don't yet provide
pipeline information.

This code also didn't have the benefit of register pressure
information. Also, removing it will avoid problems with list-burr
suddenly starting to do latency-oriented scheduling on x86 when we
start providing pipeline data, which would increase spilling.

llvm-svn: 59775

some of the latency computation logic out of the SDNode
ScheduleDAG code into a TargetInstrItineraries helper method
to help with this.

llvm-svn: 59761

condition in an addition operation.

llvm-svn: 59760

the RR scheduler actually does look at latency values, but it
doesn't use a hazard recognizer so it has no way to know when
a no-op is needed, as opposed to just stalling and incrementing
the cycle count.

llvm-svn: 59759

MachineInstr scheduling DAG, meaning they implicitly depend on all
preceding defs. This fixes Benchmarks/Shootout-C++/except and
Regression/C++/EH/simple_rethrow in
  -relocation-model=pic -disable-post-RA-scheduler=false
mode.

llvm-svn: 59747

llvm-svn: 59746

llvm-svn: 59727

llvm-svn: 59718

llvm-svn: 59702

list-tdrr schedulers into a common base class.

llvm-svn: 59701

dedicated "fast" scheduler in -fast mode instead, which is
faster. This speeds up llc -fast by a few percent on some
testcases -- the speedup only happens for code not handled by
fast-isel.

llvm-svn: 59700

the list-burr scheduler so that it can be used by the list-tdrr
scheduler too.

llvm-svn: 59698

- Register scavenger should use MachineRegisterInfo and internal map to find the first use of a register after a given machine instruction.
- When scavenging a register, in addition to the spill, insert a restore before the first use.
- Abort if client is looking to scavenge a register even when a previously scavenged register is still live.

llvm-svn: 59697

llvm-svn: 59692

extend it a bit, and make use of it in all schedulers, to
ensure consistent checking.

llvm-svn: 59689

and CreateClone don't add any extra value.

llvm-svn: 59679

is currently off by default, and can be enabled with
-disable-post-RA-scheduler=false.

This doesn't have a significant impact on most code yet because it doesn't
yet do anything to address anti-dependencies and it doesn't attempt to
disambiguate memory references. Also, several popular targets
don't have pipeline descriptions yet.

The majority of the changes here are splitting the SelectionDAG-specific
code out of ScheduleDAG, so that ScheduleDAG can be moved to
libLLVMCodeGen.a. The interface between ScheduleDAG-using code and
the rest of the scheduling code is somewhat rough and will evolve.

llvm-svn: 59676

a virtual method of SelectionDAG.

llvm-svn: 59667

dump in terms of it.

llvm-svn: 59665

llvm-svn: 59629

llvm-svn: 59587

llvm-svn: 59580

print in the correct order.

llvm-svn: 59567

llvm-svn: 59566

llvm-svn: 59562

Register scavenger should process early clobber defs first. A dead early clobber def should not interfere with a normal def which happens one slot later.

llvm-svn: 59559

consistent with ScheduleNodeTopDown methods.

llvm-svn: 59550

llvm-svn: 59549

and FP_ROUND.  Not sure what these were doing
here - probably they were sometimes (wrongly)
created with integer operands somewhere that
has since been fixed.

llvm-svn: 59548

supposed to be any functionality change.

llvm-svn: 59545

Fix a bug introduced by my previous patch.  With this change, SPEC is now clean with prealloc splitting enabled.

llvm-svn: 59544

llvm-svn: 59542

llvm-svn: 59540

llvm-svn: 59532

SCALAR_TO_VECTOR.  I didn't add the testcase, because
once llc gets past scalar-to-vector it hits a SPU target
lowering bug and explodes.

llvm-svn: 59530

llvm-svn: 59519

when softening FNEG.

llvm-svn: 59513