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  13. Dec 20, 2013
    • Timur Iskhodzhanov's avatar
      Add the .secidx test I've forgotten to svn add in 197826 · f75e5bbe
      Timur Iskhodzhanov authored
      llvm-svn: 197828
      f75e5bbe
    • Zoran Jovanovic's avatar
      Support for microMIPS FPU instructions 1. · ce02486d
      Zoran Jovanovic authored
      llvm-svn: 197815
      ce02486d
    • Saleem Abdulrasool's avatar
      ARM IAS: add support for the .pool directive · 6e6c239e
      Saleem Abdulrasool authored
      The .pool directive is an alias for the .ltorg directive used to create a
      literal pool.  Simply treat .pool as if .ltorg was passed.
      
      llvm-svn: 197787
      6e6c239e
    • Kevin Enderby's avatar
      Un-revert: the buildbot failure in LLVM on lld-x86_64-win7 had me with · 36eba25f
      Kevin Enderby authored
      this commit as the only one on the Blamelist so I quickly reverted this.
      However it was actually Nick's change who has since fixed that issue.
      
      Original commit message:
      
      Changed the X86 assembler for intel syntax to work with directional labels.
      
      The X86 assembler as a separate code to parser the intel assembly syntax
      in X86AsmParser::ParseIntelOperand().  This did not parse directional labels.
      And if something like 1f was used as a branch target it would get an
      "Unexpected token" error.
      
      The fix starts in X86AsmParser::ParseIntelExpression() in the case for
      AsmToken::Integer, it needs to grab the IntVal from the current token
      then look for a 'b' or 'f' following an Integer.  Then it basically needs to
      do what is done in AsmParser::parsePrimaryExpr() for directional
      labels.  It saves the MCExpr it creates in the IntelExprStateMachine
      in the Sym field.
      
      When it returns to X86AsmParser::ParseIntelOperand() it looks
      for a non-zero Sym field in the IntelExprStateMachine and if
      set it creates a memory operand not an immediate operand
      it would normally do for the Integer.
      
      rdar://14961158
      
      llvm-svn: 197744
      36eba25f
  14. Dec 19, 2013
    • Kevin Enderby's avatar
      Revert my change to the X86 assembler for intel syntax to work with · d6f2a637
      Kevin Enderby authored
      directional labels.  Because it doesn't work for windows :)
      
      llvm-svn: 197731
      d6f2a637
    • Kevin Enderby's avatar
      Changed the X86 assembler for intel syntax to work with directional labels. · 592d3ac2
      Kevin Enderby authored
      The X86 assembler has a separate code to parser the intel assembly syntax
      in X86AsmParser::ParseIntelOperand().  This did not parse directional labels.
      And if something like 1f was used as a branch target it would get an
      "Unexpected token" error.
      
      The fix starts in X86AsmParser::ParseIntelExpression() in the case for
      AsmToken::Integer, it needs to grab the IntVal from the current token
      then look for a 'b' or 'f' following the Integer.  Then it basically needs to
      do what is done in AsmParser::parsePrimaryExpr() for directional
      labels.  It saves the MCExpr it creates in the IntelExprStateMachine
      in the Sym field.
      
      When it returns to X86AsmParser::ParseIntelOperand() it looks
      for a non-zero Sym field in the IntelExprStateMachine and if
      set it creates a memory operand not an immediate operand
      it would normally do for the Integer.
      
      rdar://14961158
      
      llvm-svn: 197728
      592d3ac2
    • David Peixotto's avatar
      Implement the .ltorg directive for ARM assembly · 80c083a6
      David Peixotto authored
      This directive will write out the assembler-maintained constant
      pool for the current section. These constant pools are created to
      support the ldr-pseudo instruction (e.g. ldr r0, =val).
      
      The directive can be used by the programmer to place the constant
      pool in a location that can be reached by a pc-relative offset in
      the ldr instruction.
      
      llvm-svn: 197711
      80c083a6
    • David Peixotto's avatar
      Implement the ldr-pseudo opcode for ARM assembly · e407d093
      David Peixotto authored
      The ldr-pseudo opcode is a convenience for loading 32-bit constants.
      It is converted into a pc-relative load from a constant pool. For
      example,
      
        ldr r0, =0x10001
        ldr r1, =bar
      
      will generate this output in the final assembly
      
        ldr r0, .Ltmp0
        ldr r1, .Ltmp1
        ...
        .Ltmp0: .long 0x10001
        .Ltmp1: .long bar
      
      Sketch of the LDR pseudo implementation:
        Keep a map from Section => ConstantPool
      
        When parsing ldr r0, =val
          parse val as an MCExpr
          get ConstantPool for current Section
          Label = CreateTempSymbol()
          remember val in ConstantPool at next free slot
          add operand to ldr that is MCSymbolRef of Label
      
        On finishParse() callback
          Write out all non-empty constant pools
          for each Entry in ConstantPool
            Emit Entry.Label
            Emit Entry.Value
      
      Possible improvements to be added in a later patch:
        1. Does not convert load of small constants to mov
           (e.g. ldr r0, =0x1 => mov r0, 0x1)
        2. Does reuse constant pool entries for same constant
      
      The implementation was tested for ARM, Thumb1, and Thumb2 targets on
      linux and darwin.
      
      llvm-svn: 197708
      e407d093
    • Zoran Jovanovic's avatar
      Support for microMIPS control instructions. · 8e918c3c
      Zoran Jovanovic authored
      llvm-svn: 197696
      8e918c3c
    • Hal Finkel's avatar
      Add a disassembler to the PowerPC backend · 2345347e
      Hal Finkel authored
      The tests for the disassembler were adapted from the encoder tests, and for the
      most part, the output from the disassembler matches that encoder-test inputs.
      There are some places where more-informative mnemonics could be produced
      (notably for the branch instructions), and those cases are noted in the tests
      with FIXMEs.
      
      Future work includes:
      
       - Generating more-informative mnemonics when possible (this may also be done
         in the printer).
      
       - Remove the dependence on positional "numbered" operand-to-variable mapping
         (for both encoding and decoding).
      
       - Internally using 64-bit instruction variants in 64-bit mode (if this turns
         out to matter).
      
      llvm-svn: 197693
      2345347e
    • Zoran Jovanovic's avatar
      Support for microMIPS LL and SC instructions. · ff9d5f32
      Zoran Jovanovic authored
      llvm-svn: 197692
      ff9d5f32
    • Zoran Jovanovic's avatar
      Support for microMIPS TLS relocations. · 69be811a
      Zoran Jovanovic authored
      llvm-svn: 197685
      69be811a
    • Saleem Abdulrasool's avatar
      ARM IAS: support .inst directive · c0da2cb3
      Saleem Abdulrasool authored
      This adds support for the .inst directive.  This is an ARM specific directive to
      indicate an instruction encoded as a constant expression.  The major difference
      between .word, .short, or .byte and .inst is that the latter will be
      disassembled as an instruction since it does not get flagged as data.
      
      llvm-svn: 197657
      c0da2cb3
  15. Dec 18, 2013
  16. Dec 17, 2013
  17. Dec 13, 2013
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