Load / store multiple instructions cannot load / store sp. Sorry, can't come up with a reasonable test case.

llvm-svn: 96023

llvm-svn: 96019

llvm-svn: 96010

llvm-svn: 95999

MRRC, MRRc2.  For disassembly only.

llvm-svn: 95955

llvm-svn: 95916

Sorry!

llvm-svn: 95892

A8.6.297

llvm-svn: 95885

llvm-svn: 95884

as the "Permanently UNDEFINED" instruction.

llvm-svn: 95873

llvm-svn: 95784

OutStreamer.AddBlankLine instead of textually.

llvm-svn: 95734

A8.6.279

llvm-svn: 95713

A8.6.335 & A8.6.336

llvm-svn: 95703

into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687

tMOVCCi pattern only valid for low registers, as the Thumb1 mov immediate to
register instruction only works with low registers. Allowing high registers
for the instruction resulted in the assembler choosing the wide (32-bit)
encoding for the mov, but LLVM though the instruction was only 16 bits wide,
so offset calculations for constant pools became incorrect, leading to
out of range constant pool entries.

llvm-svn: 95686

For disassembly only.

A8.6.300

llvm-svn: 95669

llvm-svn: 95609

llvm-svn: 95603

The 'R' suffix means the to-integer operations use the rounding mode specified
by the FPSCR, encoded as Inst{7} = 0.

A8.6.295

llvm-svn: 95584

llvm-svn: 95560

A8.6.331 VMOV (between two ARM core registers and two single-precision registers)

llvm-svn: 95548

Radar 7614112.

llvm-svn: 95456

llvm-svn: 95397

of const ones.  non-const ones aren't very useful, because you can't
even, say, emit them.

llvm-svn: 95205

llvm-svn: 95181

the end of the instruction instead of expecting the caller to
do it.  This currently causes the asm-verbose instruction 
comments to be on the next line.

llvm-svn: 95178

than DEBUG_VALUE :(  ) into the target indep AsmPrinter.cpp
file.   This allows elimination of the 
NO_ASM_WRITER_BOILERPLATE hack among other things.

llvm-svn: 95177

even when -disable-fp-elim is specified.

llvm-svn: 95161

llvm-svn: 95160

mccontext instead of having AsmPrinter do it.  This allows other 
types of MCStreamer's to be passed in.

llvm-svn: 95155

llvm-svn: 95146

llvm-svn: 95138

llvm-svn: 95134

eliminate random "code emitter" stuff in Alpha, except for
the JIT path.  Next up, remove the template cruft.

llvm-svn: 95131

llvm-svn: 95130

llvm-svn: 95112

Rn operand.

llvm-svn: 95025

llvm-svn: 94955

Even if they are suported by the core, they can be disabled
(this is just a configuration bit inside some register).

Allow unaligned memops on darwin and conservatively disallow them otherwise.

llvm-svn: 94889