The register allocators don't currently support adding reserved
registers while they are running.  Extend the MRI API to keep track of
the set of reserved registers when register allocation started.

Target hooks like hasFP() and needsStackRealignment() can look at this
set to avoid reserving more registers during register allocation.

llvm-svn: 147577

Values, rather than just Instructions, since it's interesting
for ConstantExprs too.

llvm-svn: 147560

llvm-svn: 147553

Get back getHostTriple.

For JIT compilation, use the host triple instead of the default
target: this fixes some JIT testcases that used to fail when the
compiler has been configured as a cross compiler.

llvm-svn: 147542

llvm-svn: 147541

llvm-svn: 147529

nsw bits on them.

llvm-svn: 147528

Allow vector shuffle normalizing to use concat vector even if the sources are commuted in the shuffle mask.

llvm-svn: 147527

llvm-svn: 147525

llvm-svn: 147519

  versions derive from them.
- JALR64 is not needed since N64 does not emit jal. 
- Add template parameter to BranchLink that sets the rt field. 
- Fix the set of temporary registers for O32 and N64.

llvm-svn: 147518

is Mips64.

llvm-svn: 147516

llvm-svn: 147513

(x > y) ? x : y
=>
(x >= y) ? x : y

So for something like
(x - y) > 0 : (x - y) ? 0
It will be
(x - y) >= 0 : (x - y) ? 0

This makes is possible to test sign-bit and eliminate a comparison against
zero. e.g.
subl   %esi, %edi
testl  %edi, %edi
movl   $0, %eax
cmovgl %edi, %eax
=>
xorl   %eax, %eax
subl   %esi, $edi
cmovsl %eax, %edi

rdar://10633221

llvm-svn: 147512

Before we'd get:

$ clang t.c 
fatal error: error in backend: Invalid operand for inline asm constraint 'i'!

Now we get:

$ clang t.c
t.c:16:5: error: invalid operand for inline asm constraint 'i'!
    "movq         (%4), %%mm0\n"
    ^

Which at least gets us the inline asm that is the problem.

llvm-svn: 147502

llvm-svn: 147501

llvm-svn: 147495

This patch caused a miscompilation of oggenc because a frame pointer was
suddenly needed halfway through register allocation.

<rdar://problem/10625436>

llvm-svn: 147487

This can only happen if the set of reserved registers changes during
register allocation.

<rdar://problem/10625436>

llvm-svn: 147486

llvm-svn: 147485

llvm-svn: 147484

then a vxorps + vinsertf128 pair if the original vector came from a load.
rdar://10594409

llvm-svn: 147481

if-statement by turning it into an assert. No functionality change.

llvm-svn: 147474

Remove the restriction that target intrinsics can only involve legal types.  Targets can perfects well support intrinsics on illegal types, as long as they are prepared to perform custom expansion during type legalization.  For example, a target where i64 is illegal might still support the i64 intrinsic operation using pairs of i32's.  ARM already does some expansions like this for non-intrinsic operations.

llvm-svn: 147472

llvm-svn: 147471

If anybody has strong feelings about 'default: assert(0 && "blah")' vs
'default: llvm_unreachable("blah")', feel free to regularize the instances of
each in this file.

llvm-svn: 147459

llvm-svn: 147454

llvm-svn: 147453

llvm-svn: 147446

The failure seen on win32, when i64 type is illegal.
It happens on stage of conversion VECTOR_SHUFFLE to BUILD_VECTOR.

The failure message is:
llc: SelectionDAG.cpp:784: void VerifyNodeCommon(llvm::SDNode*): Assertion `(I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && EltVT.bitsLE(I->getValueType()))) && "Wrong operand type!"' failed.

I added a special test that checks vector shuffle on win32.

llvm-svn: 147445

"phony" insertion point.

Fixes rdar://10619599: "SelectionDAGBuilder shouldn't visit PHI nodes!" assert

llvm-svn: 147439

Miscellaneous shuffle lowering cleanup. No functional changes. Primarily converting the indexing loops to unsigned to be consistent across functions.

llvm-svn: 147430

Make CanXFormVExtractWithShuffleIntoLoad reject loads with multiple uses. Also make it return false if there's not even a load at all. This makes the code better match the code in DAGCombiner that it tries to match. These two changes prevent some cases where vector_shuffles were making it to instruction selection and causing the older shuffle selection code to be triggered. Also needed to fix a bad pattern that this change exposed. This is the first step towards getting rid of the old shuffle selection support. No test cases yet because there's no way to tell whether a shuffle was handled in the legalize stage or at instruction selection.

llvm-svn: 147428

Optimize the sequence blend(sign_extend(x)) to blend(shl(x)) since SSE blend instructions only look at the highest bit.

llvm-svn: 147426

PR11677.

llvm-svn: 147425

llvm-svn: 147411

Fix sfence, lfence, mfence, and clflush to be able to be selected when AVX is enabled. Fix monitor and mwait to require SSE3 or AVX, previously they worked even if SSE3 was disabled. Make prefetch instructions not set the execution domain since they don't use XMM registers.

llvm-svn: 147409

llvm-svn: 147404

PatternMatch: Introduce a matcher for instructions with the "exact" bit. Use it to simplify a few matchers.

llvm-svn: 147403

llvm-svn: 147400