'invoke' instruction. You will get a situation like this:

bb:
  %ehptr = eh.exception()
  %sel = eh.selector(%ehptr, @per, 0);

...

bb2:
  invoke _Unwind_Resume_or_Rethrow(%ehptr) %normal unwind to %lpad

lpad:
  ...

The unwinder will see the %sel call as a clean-up and, if it doesn't have a
catch further up the call stack, it will skip running it. But there *is* another
catch up the stack -- the catch for the %lpad. However, we can't see that. This
is fixed in code-gen, where we detect this situation, and convert the "clean-up"
selector call into a "catch-all" selector call. This gives us the correct
semantics.

llvm-svn: 99671

to encode the byte location of the extracted result in the concatenation of the
operands, from the least significant end.

Modify VEXTd and VEXTq classes to use the format.

llvm-svn: 99659

in the header.  How can both clang and gcc accept this?

PR6703

llvm-svn: 99658

llvm-svn: 99656

follow the N3RegFrm's operand order of D:Vd N:Vn M:Vm.  The operand order of
N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the first src operand).

Add a parent class N3Vf which requires passing a Format argument and which the
N3V class is modified to inherit from.  N3V class represents the "normal"
3-Register NEON Instructions with N3RegFrm.

Also add a multiclass N3VSh_QHSD to represent clusters of NEON 3-Register Shift
Instructions and replace 8 invocations with it.

llvm-svn: 99655

llvm-svn: 99637

Radar 7797856

llvm-svn: 99630

Examples are VABA (Vector Absolute Difference and Accumulate), VABAL (Vector
Absolute Difference and Accumulate Long), and VABD (Vector Absolute Difference).

llvm-svn: 99628

llvm-svn: 99620

llvm-svn: 99598

LiveVariables should clear kill / dead markers first. This allows us to remove a hack in the scheduler.

llvm-svn: 99597

dispatch to the appropriate routines to handle the different interpretations of
the shift amount encoded in the imm6 field.  The Vd, Vm fields are interpreted
the same between the two, though.

See, for example, A8.6.367 VQSHL, VQSHLU (immediate) for N2RegVShLFrm format and
A8.6.368 VQSHRN, VQSHRUN for N2RegVShRFrm format.

llvm-svn: 99590

llvm-svn: 99589

llvm-svn: 99580

Try trivial remat before the coalescer gives up on a vr / physreg coalescing for fear of tying up a physical register.

llvm-svn: 99575

llvm-svn: 99573

Re-commit. This time complete with testsuite updates.

llvm-svn: 99570

llvm-svn: 99569

llvm-svn: 99568

llvm-svn: 99567

It doesn't seem to be used anywhere.

llvm-svn: 99566

llvm-svn: 99565

llvm-svn: 99564

exactly two passes in that case, and don't ever need to recompute any layout,
so this is a nice baseline for relaxation performance.

llvm-svn: 99563

llvm-svn: 99557

llvm-svn: 99549

expect a Format arg.  N2VCvtD/N2VCvtQ are modified to use the NVCVTFrm format.

llvm-svn: 99548

llvm-svn: 99544

 - Still O(N^2), just a faster form, and now its the MCAsmLayout's fault.

On the .s I am tuning against (combine.s from 403.gcc):
--
ddunbar@lordcrumb:MC$ diff stats-before.txt stats-after.txt
5,10c5,10
<    1728 assembler - Number of assembler layout and relaxation steps
<    7707 assembler - Number of emitted assembler fragments
<  120588 assembler - Number of emitted object file bytes
< 2233448 assembler - Number of evaluated fixups
<    1727 assembler - Number of relaxed instructions
< 6723845 mcexpr    - Number of MCExpr evaluations
---
>      3 assembler - Number of assembler layout and relaxation steps
>   7707 assembler - Number of emitted assembler fragments
> 120588 assembler - Number of emitted object file bytes
>  14796 assembler - Number of evaluated fixups
>   1727 assembler - Number of relaxed instructions
>  67889 mcexpr    - Number of MCExpr evaluations
--
Feel free to LOL at the -before numbers, if you like.

I am a little surprised we make more than 2 relaxation passes. It's pretty
trivial for us to do relaxation out-of-order if that would give a speedup.

llvm-svn: 99543

llvm-svn: 99542

llvm-svn: 99540

Remove much horribleness from X86InstrFormats as a result. Similar
simplifications are probably possible for other targets.

llvm-svn: 99539

the custom insertion hook deletes the instruction, then we try to set dead
flags on it.  Neither the code that I added nor the code that was there 
before was safe.

llvm-svn: 99538

llvm-svn: 99537

llvm-svn: 99529

llvm-svn: 99528

On Nehalem and newer CPUs there is a 2 cycle latency penalty on using a register
in a different domain than where it was defined. Some instructions have
equvivalents for different domains, like por/orps/orpd.

The SSEDomainFix pass tries to minimize the number of domain crossings by
changing between equvivalent opcodes where possible.

This is a work in progress, in particular the pass doesn't do anything yet. SSE
instructions are tagged with their execution domain in TableGen using the last
two bits of TSFlags. Note that not all instructions are tagged correctly. Life
just isn't that simple.

The SSE execution domain issue is very similar to the ARM NEON/VFP pipeline
issue handled by NEONMoveFixPass. This pass may become target independent to
handle both.

llvm-svn: 99524

instead of the current N2V.  Format of NVDupLane instances are set to NEONFrm
currently.

llvm-svn: 99518

opcode values fitting in one byte (svn r99494).

llvm-svn: 99514

llvm-svn: 99507