- Mar 24, 2009
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Misha Brukman authored
llvm-svn: 67652
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Duncan Sands authored
The configure line had --disable-bootstrap, but it was not clear that this is essential. llvm-svn: 67651
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Evan Cheng authored
llvm-svn: 67649
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Dan Gohman authored
llvm-svn: 67647
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Gabor Greif authored
llvm-svn: 67642
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Chris Lattner authored
to/from integer types that are not intptr_t to convert to intptr_t then do an integer conversion to the dest type. This exposes the cast to the optimizer. llvm-svn: 67638
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Dale Johannesen authored
and streamline code here a bit. llvm-svn: 67636
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Chris Lattner authored
1. Make instcombine always canonicalize trunc x to i1 into an icmp(x&1). This exposes the AND to other instcombine xforms and is more of what the code generator expects. 2. Rewrite the remaining trunc pattern match to use 'match', which simplifies it a lot. llvm-svn: 67635
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Dale Johannesen authored
llvm-svn: 67629
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Dan Gohman authored
llvm-svn: 67622
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Chris Lattner authored
the target constraint specifies a specific physreg. llvm-svn: 67618
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Chris Lattner authored
llvm-svn: 67617
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Chris Lattner authored
fail. llvm-svn: 67616
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Dan Gohman authored
to be returned in DL. LLVM's multiple-return-value support is not ABI-conforming; front-ends that wish to have code emitted that conforms to an ABI are currently expected to make arrangements for this on their own rather than assuming that multiple-return-values will automatically do the right thing. This commit doesn't fundamentally change this situation. llvm-svn: 67588
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Dan Gohman authored
canClobberPhysRegDefs if the successor node doesn't clobber any physical registers. llvm-svn: 67587
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Dan Gohman authored
help out the register pressure reduction heuristics in the case of nodes with multiple uses. Currently this uses very conservative heuristics, so it doesn't have a broad impact, but in cases where it does help it can make a big difference. llvm-svn: 67586
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Evan Cheng authored
llvm-svn: 67580
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Dale Johannesen authored
llvm-svn: 67578
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- Mar 23, 2009
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Evan Cheng authored
Fix a bug in spill weight computation. If the alias is a super-register, and the super-register is in the register class we are trying to allocate. Then add the weight to all sub-registers of the super-register even if they are not aliases. e.g. allocating for GR32, bh is not used, updating bl spill weight. bl should get the same spill weight otherwise it will be choosen as a spill candidate since spilling bh doesn't make ebx available. This fix PR2866. llvm-svn: 67574
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Ted Kremenek authored
llvm-svn: 67565
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Dale Johannesen authored
same as a normal i80 {low64, high16} rather than its own {high64, low16}. A depressing number of places know about this; I think I got them all. Bitcode readers and writers convert back to the old form to avoid breaking compatibility. llvm-svn: 67562
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John Mosby authored
llvm-svn: 67560
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Dan Gohman authored
a data dependency on the load node, so it really needs a data-dependence edge to the load node, even if the load previously existed. And add a few comments. llvm-svn: 67554
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Evan Cheng authored
llvm-svn: 67545
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Evan Cheng authored
llvm-svn: 67544
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Dan Gohman authored
actually have uses, which reflects the way it's used. llvm-svn: 67540
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Dan Gohman authored
in an SUnit, instead of just the first one. This fix is needed by some upcoming scheduler changes. llvm-svn: 67531
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Dan Gohman authored
defs, regardless of whether they are actually used. llvm-svn: 67528
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Dan Gohman authored
explicitly flush it. llvm-svn: 67526
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Dan Gohman authored
llvm-svn: 67525
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Dan Gohman authored
llvm-svn: 67524
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Dan Gohman authored
llvm-svn: 67523
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Dan Gohman authored
static member functions, and add getIncomingValueNumForOperand and getIncomingBlockNumForOperand, which are the respective inverses. llvm-svn: 67522
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Dan Gohman authored
llvm-svn: 67518
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Evan Cheng authored
Model inline asm constraint which ties an input to an output register as machine operand TIED_TO constraint. This eliminated the need to pre-allocate registers for these. This also allows register allocator can eliminate the unneeded copies. llvm-svn: 67512
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Evan Cheng authored
Do not fold away subreg_to_reg if the source register has a sub-register index. That means the source register is taking a sub-register of a larger register. e.g. On x86 %RAX<def> = ... %RAX<def> = SUBREG_TO_REG 0, %EAX:3<kill>, 3 The first def is defining RAX, not EAX so the top bits were not zero-extended. llvm-svn: 67511
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Chris Lattner authored
llvm-svn: 67510
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Chris Lattner authored
were when we came around, not to their default handler. This should fix PR3848 llvm-svn: 67509
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Chris Lattner authored
llvm-svn: 67508
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Dan Gohman authored
llvm-svn: 67507
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