llvm-svn: 27457

llvm-svn: 27453

lower it and LLVM to have one fewer intrinsic.  This implements
CodeGen/PowerPC/vec_shuffle.ll

llvm-svn: 27450

vperm with a perm mask lvx'd from the constant pool.

llvm-svn: 27448

llvm-svn: 27442

llvm-svn: 27440

llvm-svn: 27439

llvm-svn: 27433

llvm-svn: 27425

llvm-svn: 27423

llvm-svn: 27421

llvm-svn: 27419

llvm-svn: 27418

llvm-svn: 27417

llvm-svn: 27416

llvm-svn: 27414

Fix some broken logic that would cause us to codegen {2147483647,2147483647,2147483647,2147483647} as 'vspltisb v0, -1'.

llvm-svn: 27413

handle all 4 PPC vector types.   This simplifies the matching code and allows
us to eliminate a bunch of patterns.  This also adds cases we were missing,
such as CodeGen/PowerPC/vec_splat.ll:splat_h.

llvm-svn: 27400

llvm-svn: 27387

llvm-svn: 27386

llvm-svn: 27385

more than the OS keeps the stack aligned.

llvm-svn: 27381

llvm-svn: 27372

llvm-svn: 27360

llvm-svn: 27359

llvm-svn: 27351

llvm-svn: 27348

"vspltisb v0, 8" instead of a constant pool load.

llvm-svn: 27335

llvm-svn: 27331

llvm-svn: 27322

No functionality change.

llvm-svn: 27320

llvm-svn: 27315

llvm-svn: 27308

llvm-svn: 27307

llvm-svn: 27306

llvm-svn: 27305

llvm-svn: 27302

llvm-svn: 27291

identical instructions into a single instruction.  For example, for:

void test(vector float *x, vector float *y, int *P) {
  int v = vec_any_out(*x, *y);
  *x = (vector float)vec_cmpb(*x, *y);
  *P = v;
}

we now generate:

_test:
        mfspr r2, 256
        oris r6, r2, 49152
        mtspr 256, r6
        lvx v0, 0, r4
        lvx v1, 0, r3
        vcmpbfp. v0, v1, v0
        mfcr r4, 2
        stvx v0, 0, r3
        rlwinm r3, r4, 27, 31, 31
        xori r3, r3, 1
        stw r3, 0(r5)
        mtspr 256, r2
        blr

instead of:

_test:
        mfspr r2, 256
        oris r6, r2, 57344
        mtspr 256, r6
        lvx v0, 0, r4
        lvx v1, 0, r3
        vcmpbfp. v2, v1, v0
        mfcr r4, 2
***     vcmpbfp v0, v1, v0
        rlwinm r4, r4, 27, 31, 31
        stvx v0, 0, r3
        xori r3, r4, 1
        stw r3, 0(r5)
        mtspr 256, r2
        blr

Testcase here: CodeGen/PowerPC/vcmp-fold.ll

llvm-svn: 27290

llvm-svn: 27288