- Sep 25, 2013
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Andrew Trick authored
This is being disabled because it is no longer needed for performance. It is only used by postRAscheduler which is also planned for removal, and it is implemented with an out-dated view of register liveness. It consideres aliases instead of register units, assumes valid kill flags, and assumes implicit uses on partial register defs. Kill flags and implicit operands are error prone and impossible to verify. We should gradually eliminate dependence on them in the postRA phases. Targets that still benefit from this should move to the MI scheduler. If that doesn't solve the problem, then we should add a hook to regalloc to optimize reload placement. llvm-svn: 191348
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Jim Grosbach authored
Give the symbol's name and disengage the enchanced crash reporting. llvm-svn: 191344
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Peter Collingbourne authored
more reliably across platforms. Patch by Tom Roeder! llvm-svn: 191343
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Eli Friedman authored
PR17338. llvm-svn: 191337
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- Sep 24, 2013
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David Blaikie authored
llvm-svn: 191333
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David Blaikie authored
CR feedback from Eric Christopher llvm-svn: 191330
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David Blaikie authored
llvm-svn: 191329
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Yunzhong Gao authored
Adding TBM feature to bdver2 processor; piledriver supports this instruction set according to the following document: http://developer.amd.com/wordpress/media/2012/10/New-Bulldozer-and-Piledriver-Instructions.pdf Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1692 llvm-svn: 191324
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Benjamin Kramer authored
This code isn't ready to deal with allocation functions where the return is not the allocated pointer. The checks below will reject posix_memalign anyways. llvm-svn: 191319
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Roman Divacky authored
llvm-svn: 191318
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Benjamin Kramer authored
llvm-svn: 191315
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Yi Jiang authored
llvm-svn: 191314
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Benjamin Kramer authored
We really don't want to optimize malloc return value checks away. llvm-svn: 191313
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Andrew Trick authored
llvm-svn: 191312
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Benjamin Kramer authored
This is safe per C++11 18.6.1.1p3: [operator new returns] a non-null pointer to suitably aligned storage (3.7.4), or else throw a bad_alloc exception. This requirement is binding on a replacement version of this function. Brings us a tiny bit closer to eliminating more vector push_backs. llvm-svn: 191310
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Benjamin Kramer authored
llvm-svn: 191309
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Daniel Sanders authored
llvm-svn: 191306
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Daniel Sanders authored
[mips][msa] Added support for matching ilv[lr], ilvod, and ilvev from normal IR (i.e. not intrinsics) llvm-svn: 191304
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Benjamin Kramer authored
No functionality change, lots of indentation changes. llvm-svn: 191303
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Daniel Sanders authored
llvm-svn: 191302
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Daniel Sanders authored
llvm-svn: 191301
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Daniel Sanders authored
Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
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Daniel Sanders authored
[mips][msa] Non-constant BUILD_VECTOR's should be expanded to INSERT_VECTOR_ELT instead of memory operations. The resulting code is the same length, but doesnt cause memory traffic or latency. llvm-svn: 191297
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Daniel Sanders authored
This covers the case where fmax_a can be used to implement ISD::FABS. llvm-svn: 191296
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Daniel Sanders authored
No functional change. llvm-svn: 191295
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Daniel Sanders authored
[mips][msa] Added support for matching andi, ori, nori, and xori from normal IR (i.e. not intrinsics) llvm-svn: 191293
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Daniel Sanders authored
llvm-svn: 191291
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Daniel Sanders authored
This required correcting the definition of the bsel and bseli intrinsics. llvm-svn: 191290
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Evgeniy Stepanov authored
llvm-svn: 191287
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Daniel Sanders authored
MIPS SelectionDAG changes: * Added VCEQ, VCL[ET]_[SU] nodes to represent vector comparisons that produce a bitmask. llvm-svn: 191286
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Daniel Sanders authored
llvm-svn: 191285
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Bill Wendling authored
Make sure that the code that handles the constant addresses is run for the GEPs. This just refactors that code and then calls it for the GEPs that are collected during the iteration. <rdar://problem/12445434> llvm-svn: 191281
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NAKAMURA Takumi authored
llvm-svn: 191266
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Jiangning Liu authored
Patch by Ana Pazos. 1.Added support for v1ix and v1fx types. 2.Added Scalar Pairwise Reduce instructions. 3.Added initial implementation of Scalar Arithmetic instructions. llvm-svn: 191263
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Michael Gottesman authored
Sometimes a copy from a vreg -> vreg sneaks into the middle of a terminator sequence. It is safe to slice this into the stack protector success bb. This fixes PR16979. llvm-svn: 191260
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Eli Friedman authored
PR17317. llvm-svn: 191258
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Eric Christopher authored
llvm-svn: 191257
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Eric Christopher authored
llvm-svn: 191255
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Bill Wendling authored
The recursive nature of the address selection code can cause the stack to explode if there is a long chain of GEPs. Convert the recursive bit into a iterative method to avoid this. <rdar://problem/12445434> llvm-svn: 191252
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David Blaikie authored
llvm-svn: 191244
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