llvm-svn: 42179

isRegister, isImmediate, and isMachineBasicBlock, which are equivalent,
and more popular.

llvm-svn: 41958

llvm-svn: 41947

llvm-svn: 41873

llvm-svn: 41863

init_trampoline.  There is now only one
trampoline intrinsic.

llvm-svn: 41841

llvm-svn: 41808

llvm-svn: 41776

Patch by Sterling Stein!

llvm-svn: 41758

llvm-svn: 41733

llvm-svn: 41717

llvm-svn: 41711

Use APFloat interfaces for more references, mostly
of ConstantFPSDNode.

llvm-svn: 41632

Add a variant of foldMemoryOperand to fold any load / store, not just load / store from / to stack slots.

llvm-svn: 41597

llvm-svn: 41590

changing the interface to allow for future changes.

llvm-svn: 41384

llvm-svn: 41360

llvm-svn: 41318

llvm-svn: 40957

llvm-svn: 40908

(I've tried to get the info right for all targets,
but I'm not expert on all of them - check yours.)

llvm-svn: 40792

llvm-svn: 40757

llvm-svn: 40697

llvm-svn: 40586

still under discussion.

llvm-svn: 40549

AsmPrinter::doFinalization.

llvm-svn: 40487

llvm-svn: 40483

llvm-svn: 40132

llvm-svn: 40123

llvm-svn: 40074

InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033

This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.

In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.

After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be 
thought as 'finished': I expect many small and not so small glitches
everywhere.

llvm-svn: 39855

Change name of -sched option and DEBUG_TYPE to
pre-RA-sched; adjust testcases.

llvm-svn: 39816

llvm-svn: 39737

register ordering, for both physical and virtual registers. Update the PPC
target lowering for calls to expect registers for the call result to
already be in target order.

llvm-svn: 38471

zero if they see a target triple they don't understand.

llvm-svn: 38463

llvm-svn: 37961

Almost all occurrences of "bytecode" in the sources have been eliminated.

llvm-svn: 37913

llvm-svn: 37893

llvm-svn: 37801