TargetLoweringObjectFileImpl down to MCObjectFileInfo.

TargetAsmInfo is done to one last method. It's *almost* gone!

llvm-svn: 135569

X86Subtarget.h: Assume "x86_64-cygwin", though it has not been released yet, to appease test/CodeGen/X86 on cygwin.

llvm-svn: 135564

llvm-svn: 135555

llvm-svn: 135550

llvm-svn: 135546

llvm-svn: 135537

The system register spec should be case insensitive. The preferred form for
output with mask values of 4, 8, and 12 references APSR rather than CPSR.
Update and tidy up tests accordingly.

llvm-svn: 135532

Teach the parser to recognize the APSR and SPSR system register names. Add
and update tests accordingly.

llvm-svn: 135527

llvm-svn: 135524

llvm-svn: 135522

Add range checking to the immediate operands. Update tests accordingly.

llvm-svn: 135521

ANDi, when the instruction does not have any immediate operands.

llvm-svn: 135520

llvm-svn: 135514

Correct the handling of the 's' suffix when parsing ARM mode. It's only a
truly separate opcode in Thumb. Add test cases to make sure we handle
the s and condition suffices correctly, including diagnostics.

llvm-svn: 135513

llvm-svn: 135507

Make sure we only clobber the cc_out operand if it is indeed a default
non-setting operand.

llvm-svn: 135506

Add range checking for the immediate operand and handle the "mov" mnemonic
choosing between encodings based on the value of the immediate. Add tests
for fixups, encoding choice and values, and diagnostic for out of range values.

llvm-svn: 135500

cc_out and pred operands are added during parsing via custom C++ now.

llvm-svn: 135497

llvm-svn: 135496

- In EmitAtomicBinaryPartword, mask incr in loopMBB only if atomic.swap is the
  instruction being expanded, instead of masking it in thisMBB. 
- Remove redundant Or in EmitAtomicCmpSwap. 

llvm-svn: 135495

basic blocks.

llvm-svn: 135490

llvm-svn: 135489

llvm-svn: 135481

llvm-svn: 135478

llvm-svn: 135476

llvm-svn: 135475

llvm-svn: 135474

(including compilation, assembly). Move relocation model Reloc::Model from
TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine.

llvm-svn: 135468

ExpandISelPseudos::runOnMachineFunction does not visit instructions that have
just been added.

llvm-svn: 135465

llvm-svn: 135464

Revamp our handling of tLDMIA[_UPD] and tSTMIA[_UPD] to avoid having multiple instructions with the same encoding.  This resolves another conflict when bringing up the new-style disassembler.

llvm-svn: 135442

use of TargetFrameLowering in TargetAsmInfo.

llvm-svn: 135439

better location welcome).

llvm-svn: 135438

Mark the Darwin assembler workout as isCodeGenOnly, so that it doesn't cause decoding conflicts in the new-style disassembler.

llvm-svn: 135434

to MCRegisterInfo. Also initialize the mapping at construction time.

This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.

llvm-svn: 135424

llvm-svn: 135418

moving them out of the loop. Previously, stores and loads to a stack frame
object were inserted to accomplish this. Remove the code that was needed to do
this. Patch by Sasa Stankovic.

llvm-svn: 135415

Original Log: Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode.  Update the ARM disassembler for this change.

llvm-svn: 135414

definitions.

llvm-svn: 135407

llvm-svn: 135404