- Aug 12, 2010
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Nick Lewycky authored
- remove ashr which never worked. - fix lshr and shl and add tests. - remove dead function "intersect1Wrapped". - add a new sub method to subtract ranges, with test. llvm-svn: 110861
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- Aug 11, 2010
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Bruno Cardoso Lopes authored
llvm-svn: 110854
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Dan Gohman authored
and remove casts from all its callers. llvm-svn: 110848
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Dan Gohman authored
llvm-svn: 110847
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Bruno Cardoso Lopes authored
llvm-svn: 110845
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Dan Gohman authored
llvm-svn: 110843
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Dan Gohman authored
llvm-svn: 110842
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Dan Gohman authored
that many of these things, so the memory savings isn't significant, and there are now situations where there can be alignments greater than 128. llvm-svn: 110836
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Dan Gohman authored
avoids trouble if the return type of TD->getPointerSize() is changed to something which doesn't promote to a signed type, and is simpler anyway. Also, use getCopyFromReg instead of getRegister to read a physical register's value. llvm-svn: 110835
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Bruno Cardoso Lopes authored
llvm-svn: 110833
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Jim Grosbach authored
llvm-svn: 110831
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Jim Grosbach authored
platform. It's apparently "bl __muldf3" on linux, for example. Since that's not what we're checking here, it's more robust to just force a triple. We just wwant to check that the inline FP instructions are only generated on cpus that have them." llvm-svn: 110830
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Evan Cheng authored
llvm-svn: 110829
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Jakob Stoklund Olesen authored
llvm-svn: 110826
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Dan Gohman authored
properly investigated. llvm-svn: 110825
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Jim Grosbach authored
llvm-svn: 110810
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Dan Gohman authored
properly investigated. llvm-svn: 110808
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Bill Wendling authored
float t1(int argc) { return (argc == 1123) ? 1.234f : 2.38213f; } We would generate truly awful code on ARM (those with a weak stomach should look away): _t1: movw r1, #1123 movs r2, #1 movs r3, #0 cmp r0, r1 mov.w r0, #0 it eq moveq r0, r2 movs r1, #4 cmp r0, #0 it ne movne r3, r1 adr r0, #LCPI1_0 ldr r0, [r0, r3] bx lr The problem was that legalization was creating a cascade of SELECT_CC nodes, for for the comparison of "argc == 1123" which was fed into a SELECT node for the ?: statement which was itself converted to a SELECT_CC node. This is because the ARM back-end doesn't have custom lowering for SELECT nodes, so it used the default "Expand". I added a fairly simple "LowerSELECT" to the ARM back-end. It takes care of this testcase, but can obviously be expanded to include more cases. Now we generate this, which looks optimal to me: _t1: movw r1, #1123 movs r2, #0 cmp r0, r1 adr r0, #LCPI0_0 it eq moveq r2, #4 ldr r0, [r0, r2] bx lr .align 2 LCPI0_0: .long 1075344593 @ float 2.382130e+00 .long 1067316150 @ float 1.234000e+00 llvm-svn: 110799
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Evan Cheng authored
Report error if codegen tries to instantiate a ARM target when the cpu does support it. e.g. cortex-m* processors. llvm-svn: 110798
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Evan Cheng authored
llvm-svn: 110797
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Evan Cheng authored
llvm-svn: 110796
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Evan Cheng authored
llvm-svn: 110795
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Daniel Dunbar authored
MC/ARM: Add basic support for handling predication by parsing it out of the mnemonic into a separate operand form. llvm-svn: 110794
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Daniel Dunbar authored
llvm-svn: 110793
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Daniel Dunbar authored
llvm-svn: 110792
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Daniel Dunbar authored
llvm-mc: Add -show-inst-operands, for dumping the parsed instruction representation before matching. llvm-svn: 110791
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Daniel Dunbar authored
llvm-svn: 110790
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Daniel Dunbar authored
llvm-svn: 110789
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Daniel Dunbar authored
llvm-svn: 110788
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Evan Cheng authored
llvm-svn: 110787
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Evan Cheng authored
instructions: dmb, dsb, isb, msr, and mrs. llvm-svn: 110786
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Evan Cheng authored
memory and synchronization barrier dmb and dsb instructions. - Change instruction names to something more sensible (matching name of actual instructions). - Added tests for memory barrier codegen. llvm-svn: 110785
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Daniel Dunbar authored
llvm-svn: 110783
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Daniel Dunbar authored
llvm-svn: 110782
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Daniel Dunbar authored
for some reason they have a very odd MCInst form where the operands overlap, but I haven't dug in to find out why yet. llvm-svn: 110781
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Daniel Dunbar authored
llvm-svn: 110780
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Daniel Dunbar authored
llvm-svn: 110779
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Owen Anderson authored
llvm-svn: 110778
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Bruno Cardoso Lopes authored
llvm-svn: 110772
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Bruno Cardoso Lopes authored
Remove AVX 256-bit unpack and interleave intrinsics now that clang is using __builtin_shufflevector for those llvm-svn: 110769
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