llvm-svn: 59004

llvm-svn: 58949

indirect gv reference. Please don't call it lazy.

llvm-svn: 58746

llvm-svn: 58528

llvm-svn: 58141

fixes a bunch of test-suite JIT failures on x86-64 in
-relocation-model=static mode.

llvm-svn: 58066

Fix lfence and mfence encoding. These look like MRM5r and MRM6r instructions except they do not have any operands. The RegModRM byte is encoded with register number 0.

llvm-svn: 57692

llvm-svn: 57414

llvm-svn: 57381

llvm-svn: 57380

isReg, etc., from isRegister, etc.

llvm-svn: 57006

llvm-svn: 55779

This unbreaks explicit reg vars inside JIT, which are
implemented in such hacky way :)

llvm-svn: 55128

llvm-svn: 55117

llvm-svn: 54700

non_lazy_ptr mechanism on x86-64 Darwin JIT.  Fixes a bunch
of last night's failures.

llvm-svn: 54692

model, except for external calls; this makes
addressing modes PC-relative.  Incomplete.

The assertion at the top of Emitter::runOnMachineFunction
was obviously bogus (always true) so I removed it.
If someone knows what the correct test should be to cover
all the various targets, please fix.

llvm-svn: 54656

the need for a flavor operand, and add a new SDNode subclass,
LabelSDNode, for use with them to eliminate the need for a label id
operand.

Change instruction selection to let these label nodes through
unmodified instead of creating copies of them. Teach the MachineInstr
emitter how to emit a MachineInstr directly from an ISD label node.

This avoids the need for allocating SDNodes for the label id and
flavor value, as well as SDNodes for each of the post-isel label,
label id, and label flavor.

llvm-svn: 52943

llvm-svn: 51291

This eliminates the need for several awkward casts, including
the last dynamic_cast under lib/Target.

llvm-svn: 51091

- Remove unused instructions.

llvm-svn: 49921

Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented

llvm-svn: 49809

Fix x86-64 encoding bug. REX prefix must always follow 0x0F prefix. For example, extractps in 64bit mode: 66 REX 0F 3A 17, not 66 0F 3A REX 17.

llvm-svn: 49157

llvm-svn: 48447

Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.

llvm-svn: 48380

llvm-svn: 48359

llvm-svn: 47934

llvm-svn: 47933

Add lock prefix support to x86.  Also add the instructions necessary for the atomic ops.  They are still marked pseudo, since I cannot figure out what format to use, but they are the correct opcode.

llvm-svn: 47795

llvm-svn: 47600

llvm-svn: 47079

llvm-svn: 46877

llvm-svn: 45838

Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.

llvm-svn: 45695

Evan, please review the comments I added to getNumDefs to make sure
that they are accurate, thx.

llvm-svn: 45687

llvm-svn: 45680

that it is cheap and efficient to get.

Move a variety of predicates from TargetInstrInfo into 
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around.  Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.

Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.

llvm-svn: 45674

llvm-svn: 45616

llvm-svn: 45605

llvm-svn: 45576