extract the landing pad block. Otherwise, there will be a situation where the
invoke's unwind edge lands on a non-landing pad.

We also forbid the user from extracting the landing pad block by itself. Again,
this is not a valid transformation.

llvm-svn: 140083

llvm-svn: 140079

llvm-svn: 140078

Fix an infinite loop where a transform in InstCombiner::visitAnd claims a construct is changed when it is not.  (See included testcase.)

Patch by Xiaoyi Guo.

llvm-svn: 140072

PR10955 and PR10948.

llvm-svn: 140069

Patch by Arrowdodger.

llvm-svn: 140064

llvm-svn: 140050

llvm-svn: 140047

yet legal according to comments in LegalizeDAG.cpp:227. 

Memcpy nodes created for copying byval arguments are inserted before
CALLSEQ_START.

The two failing tests reported in PR10876 pass after applying this patch.  

llvm-svn: 140046

llvm-svn: 140043

Specify an additional fixed bit in the Thumb2 SSAT encoding to prevent the decoder from emitting gibberish for this invalid encoding.

llvm-svn: 140041

Fix a typo in the bitcode reader in the handling of atomic stores.  Reported by David Meyer on llvmdev.

llvm-svn: 140040

For example, 'ldrb r9, [sp]!' is odd, but valid.

llvm-svn: 140035

Handle STRT (and friends) like LDRT (and friends) for decoding purposes.  Port over additional encoding tests to decoding tests.

llvm-svn: 140032

llvm-svn: 140029

llvm-svn: 140027

llvm-svn: 140026

llvm-svn: 140011

llvm-svn: 140003

llvm-svn: 140001

dag-combine optimization to implement the ext-load efficiently (using shuffles).

For example the type <4 x i8> is stored in memory as i32, but it needs to
find its way into a <4 x i32> register. Previously we scalarized the memory
access, now we use shuffles.

llvm-svn: 139995

llvm-svn: 139994

llvm-svn: 139993

maxps and maxpd).  This broke the sse41-blend.ll testcase by causing
maxpd to be produced rather than a cmp+blend pair, which is the reason
I tweaked it.  Gives a small speedup on doduc with dragonegg when the
GCC vectorizer is used.

llvm-svn: 139986

mayLoad = 1

llvm-svn: 139973

llvm-svn: 139972

llvm-svn: 139969

llvm-svn: 139966

llvm-svn: 139965

llvm-svn: 139964

llvm-svn: 139958

are declared with load patterns. This fix the crash in PR10941. No testcases,
since a fold is triggered and then converted back to the register form
afterwards.

llvm-svn: 139953

More addressing mode encoding bits. Handle pre increment for STR/STRB/STRH
and STR(register).

llvm-svn: 139949

llvm-svn: 139944

llvm-svn: 139943

Add aliases for STRB/STRH while there. Tests forthcoming for those.

llvm-svn: 139942

This PR basically reports a problem where a crash in generated code
happened due to %rbp being clobbered:

  pushq %rbp
  movq  %rsp, %rbp
  ....
  vmovmskps %ymm12, %ebp
  ....
  movq  %rbp, %rsp
  popq  %rbp
  ret

Since Eric's r123367 commit, the default stack alignment for x86 32-bit
has changed to be 16-bytes. Since then, the MaxStackAlignmentHeuristicPass
hasn't been really used, but with AVX it becomes useful again, since per
ABI compliance we don't always align the stack to 256-bit, but only when
there are 256-bit incoming arguments.

ReserveFP was only used by this pass, but there's no RA target hook that
uses getReserveFP() to check for the presence of FP (since nothing was
triggering the pass to run, the uses of getReserveFP() were removed
through time without being noticed). Change this pass to use
setForceFramePointer, which is properly called by MachineFunction
hasFP method.

The testcase is very big and dependent on RA, not sure if it's worth
adding to test/CodeGen/X86.

llvm-svn: 139939

llvm-svn: 139938

llvm-svn: 139929

llvm-svn: 139928