llvm-svn: 55868

llvm-svn: 55867

i32>.  This is a little messy, but it works.

We should really get rid of the intrinsics, though, since they map
perfectly well to standard LLVM instructions.

llvm-svn: 55864

llvm-svn: 55857

llvm-svn: 55855

llvm-svn: 55854

llvm-svn: 55853

llvm-svn: 55844

llvm-svn: 55840

expanding its operands.

llvm-svn: 55820

to check the result of getRegForValue before using it, and
to check for illegal operand types.

llvm-svn: 55819

llvm-svn: 55816

pool loads on X86 in fast isel.  This isn't actually used yet.

llvm-svn: 55814

llvm-svn: 55811

For whatever the reason, x86 CallingConv::Fast (i.e. fastcc) was not passing scalar arguments in registers. This patch defines a new fastcc CC which is slightly different from the FastCall CC. In addition to passing integer arguments in ECX and EDX, it also specify doubles are passed in 8-byte slots which are 8-byte aligned (instead of 4-byte aligned). This avoids a potential performance hazard where doubles span cacheline boundaries.

llvm-svn: 55807

llvm-svn: 55794

llvm-svn: 55779

llvm-svn: 55777

Dan or Evan, please review.

llvm-svn: 55764

llvm-svn: 55763

Remove code that pad number of bytes to pop for X86_FastCall CC. The code doesn't do the "aligning" for Cygwin, Mingw, and Windows. But aligning it on Darwin and Linux breaks gcc compatibility. That ruled out all the platforms we support!

llvm-svn: 55756

No functional change (and no FE change to generate them).

llvm-svn: 55753

HandlePHINodesInSuccessorBlocks that works FastISel-style. This
allows PHI nodes to be updated correctly while using FastISel.

This also involves some code reorganization; ValueMap and
MBBMap are now members of the FastISel class, so they needn't
be passed around explicitly anymore. Also, SelectInstructions
is changed to SelectInstruction, and only does one instruction
at a time.

llvm-svn: 55746

llvm-svn: 55693

Fix capitalization in #include of FastISel.h.  This unbreaks the build on case-sensitive filesystems.

llvm-svn: 55687

llvm-svn: 55685

Let tblgen only generate fastisel routines, not the class definition. This makes it easier for targets to define its own fastisel class.

llvm-svn: 55679

llvm-svn: 55588

For now, can't mark XOR64rr isAsCheapAsAMove. It's technically correct. But various passes cannot handle remating these.

llvm-svn: 55562

Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case).

llvm-svn: 55558

llvm-svn: 55553

llvm-svn: 55552

llvm-svn: 55548

llvm-svn: 55545

llvm-svn: 55521

llvm-svn: 55512

llvm-svn: 55511

llvm-svn: 55504

llvm-svn: 55486

llvm-svn: 55466