llvm-svn: 7182

llvm-svn: 7181

Also, placed DEBUG() guards around debug information so that the generated file
is much smaller and hence should be faster to preprocess/compile.

llvm-svn: 7180

masking and shifting operands directly into their place in the instruction,
instead of the old-fashioned way of ORing in each bit separately.

llvm-svn: 7179

allow, i.e. make a sequence of instructions to enable an indirect call using
jump-and-link and 2 temporary registers (which we save and ultimately restore).

Warning: if the delay slot of a function call is used to do meaningful work and
not just a NOP, this behavior is incorrect. However, the Sparc backend does not
yet utilize the delay slots effectively, so it is not necessary to make an
overly complicated algorithm for something that's not used.

llvm-svn: 7178

usage of the special file handle RTLD_SELF on Sparc/Solaris vs. 0 on Linux/x86.

llvm-svn: 7177

the program's executing image, not 0 as it is on Linux/x86 and possibly other
systems.

llvm-svn: 7176

* FP double registers are now coded correctly
* Removed function which converted registers based on register types, it was
  broken (because regTypes are broken)

llvm-svn: 7175

llvm-svn: 7174

llvm-svn: 7173

llvm-svn: 7172

Specifically, this updates libtool to version 1.5 and adds the following:
	- Added the -only-static option that we added in our previous libtool.
	- Modified the autoconf macros so that libtool uses the -G option when
	  linking on Solaris.  This allows libraries with global variables with
	  constructors to automatically run those constructors when the
	  library is dlopened().

llvm-svn: 7171

Also, make Pointer type depend on architecture.

llvm-svn: 7170

remembered in valuesStoredInFunction, but never traced at function return,
and that's too late to be finding the error anyway).
Stores trace both the value and the address being stored to,
but after some experience I think only values should be traced.
The pointer hash table just fills up far too quickly if every
store address were traced.

llvm-svn: 7169

out the entire llvm disassembly for the function at global constant-output
time, which caused the assembler to barf in 164.gzip. This fixes that
particular problem (though 164.gzip has other problems with X86 llc.)

llvm-svn: 7168

Fhourstones, McCat-vor, and many others...)

Printer.cpp: Print implicit uses for AddRegFrm instructions.  Break gas
bug workarounds up into separate stanzas of code for each bug.  Add new
workarounds for fild and fistp.

X86InstrInfo.def: Add O_ST0 implicit uses for more FP instrs where they
obviously apply. Also add PrintImplUses flags for FP instrs where they
are necessary for gas to understand the output.

llvm-svn: 7165

llvm-svn: 7161

llvm-svn: 7160

(1) Cannot use ANDN(ot), ORN, and XORN for boolean ops, only bitwise ops.

(2) Conditional move instructions must distinguish signed and unsigned
    condition codes, e.g., MOVLE vs. MOVLEU.

(3) Conditional-move-on-register was using the cond-move-on-cc opcodes,
    which produces a valid-looking instruction with bogus registers!

(4) Here's a really cute one: dividing-by-2^k for negative numbers needs to
    add 2^k-1 before shifting, not add 1 after shifting.  Sadly, these
    are the same when k=0 so our poor test case worked fine.

(5) Casting between signed and unsigned values was not correct:
    completely reimplemented.

(6) Zero-extension on unsigned values was bogus: I was only doing the
    SRL and not the SLLX before it.  Don't know WHAT I was thinking!

(7) And the most important class of changes: Sign-extensions on signed values.
    Signed values are not sign-extended after ordinary operations,
    so they must be sign-extended before the following cases:
	-- passing to an external or unknown function
	-- returning from a function
	-- using as operand 2 of DIV or REM
	-- using as either operand of condition-code setting operation
           (currently only SUBCC), with smaller than 32-bit operands


Also, a couple of improvements:

(1) Fold cast-to-bool into Not(bool).  Need to do this for And, Or, XOR also.

(2) Convert SetCC-Const into a conditional-move-on-register (case 41)
    if the constant is 0.  This was only being done for branch-on-SetCC-Const
    when the branch is folded with the SetCC-Const.

llvm-svn: 7159

llvm-svn: 7158

boolean operations: AND, OR, XOR.

llvm-svn: 7157

llvm-svn: 7156

llvm-svn: 7155

which args can be substituted: defsOnly, defsAndUses or usesOnly.

llvm-svn: 7154

llvm-svn: 7153

(1) An int CC live range must be spilled if there are any interferences,
    even if no other "neighbour" in the interf. graph has been allocated
    that reg. yet.  This is actually true of any class with only one reg!

(2) SparcIntCCRegClass::colorIGNode sets the color even if the LR must
    be spilled so that the machine-independent spill code doesn't have to
    make the machine-dependent decision of which CC name to use based on
    operand type: %xcc or %icc.  (These are two halves of the same
register.)

(3) LR->isMarkedForSpill() is no longer the same as LR->hasColor().
    These should never have been the same, and this is necessary now for #2.

(4) All RDCCR and WRCCR instructions are directly generated with the
    phony number for %ccr so that EmitAssembly/EmitBinary doesn't have to
    deal with this.

llvm-svn: 7152

(1) An int CC live range must be spilled if there are any interferences,
    even if no other "neighbour" in the interf. graph has been allocated
    that reg. yet.  This is actually true of any class with only one reg!

(2) SparcIntCCRegClass::colorIGNode sets the color even if the LR must
    be spilled so that the machine-independent spill code doesn't have to
    make the machine-dependent decision of which CC name to use based on
    operand type: %xcc or %icc.  (These are two halves of the same register.)

(3) LR->isMarkedForSpill() is no longer the same as LR->hasColor().
    These should never have been the same, and this is necessary now for #2.

(4) All RDCCR and WRCCR instructions are directly generated with the
    phony number for %ccr so that EmitAssembly/EmitBinary doesn't have to
    deal with this.

llvm-svn: 7151

llvm-svn: 7150

llvm-svn: 7149

llvm-svn: 7147

llvm-svn: 7142

in a variable assignment.

llvm-svn: 7141

llvm-svn: 7140

llvm-svn: 7139

no functionality changed.

llvm-svn: 7138

llvm-svn: 7135

Corrected capitalization of subheadings.
Created a new subsection for compiling the C front end and moved all references
to it there.
Updated the disk space requirements to reflect the need for the binary C front
end and the optional C front end source.
Added information on unpacking the distribution to the summary section.
Moved autoconf environment variables to the autoconf section.
Changed make to gmake.
Removed some of the precise directions for unpacking the archives.
Fixed some formatting inconsistencies (headings that were not centered).

llvm-svn: 7132

Unfortunately, reallocation also means that the pointer numbering will
change, so increase table size to try to avoid it.

llvm-svn: 7130

taking out the rule for compiling the test driver.
We need the native libraries for libinstr because they are directly
linked into the native CBE or LLC code.  That is the only practical
way to debug them!

llvm-svn: 7129

Also, $(RM) needs -f flag.

llvm-svn: 7128