llvm-svn: 162210

Forgetting to at least cast the result was giving us Loc/NonLoc problems
in SValBuilder (hitting an assertion). But the standard (both C and C++)
does actually guarantee that && and || will result in the actual values
1 and 0, typed as 'int' in C and 'bool' in C++, and we can easily model that.

PR13461

llvm-svn: 162209

llvm-svn: 162207

llvm-svn: 162206

- use InnerMatcher consistently, fix style violations on the way
- doxygenify code snippets across all comments
- start doxygenifying code references in text
- addeed missing Usable as: sections

llvm-svn: 162205

I also added a typemap to make DispatchInput usable in Python.

llvm-svn: 162204

llvm-svn: 162203

llvm-svn: 162202

llvm-svn: 162201

Without this patch, lib.clang_getNumCompletionChunks is called at
each _iteration_ of a 'for chunk in CompletionString' loop. Now we
call it just once.

llvm-svn: 162200

Minor refactoring: reduce code duplication by introducing a macro for dispatch_sync_f, dispatch_async_f, dispatch_barrier_async_f bodies.

llvm-svn: 162199

llvm-svn: 162198

llvm-svn: 162197

llvm-svn: 162196

The DAGCombiner tries to optimise a BUILD_VECTOR by checking if it
consists purely of get_vector_elts from one or two source vectors. If
so, it either makes a concat_vectors node or a shufflevector node.

However, it doesn't check the element type width of the underlying
vector, so if you have this sequence:

Node0: v4i16 = ...
Node1: i32 = extract_vector_elt Node0
Node2: i32 = extract_vector_elt Node0
Node3: v16i8 = BUILD_VECTOR Node1, Node2, ...

It will attempt to:

Node0:    v4i16 = ...
NewNode1: v16i8 = concat_vectors Node0, ...

Where this is actually invalid because the element width is completely
different. This causes an assertion failure on DAG legalization stage.

Fix:
If output item type of BUILD_VECTOR differs from input item type.
Make concat_vectors based on input element type and then bitcast it to the output vector type. So the case described above will transformed to:
Node0:    v4i16 = ...
NewNode1: v8i16 = concat_vectors Node0, ...
NewNode2: v16i8 = bitcast NewNode1

llvm-svn: 162195

llvm-svn: 162194

llvm-svn: 162193

llvm-svn: 162192

Suggested by:  Francisco Lopes  <oblita@gmail.com>

llvm-svn: 162191

It isn't used anywhere yet.

llvm-svn: 162190

In C++03 mode add an explicit conversion from int to the emulated class enum.  Fixes a problem reported by C. Bergström.

llvm-svn: 162189

llvm-svn: 162188

this allows for better code generation.

Added a new DAGCombine transformation to convert FMAX and FMIN to FMANC and
FMINC, which are commutative.

For example:

  movaps  %xmm0, %xmm1
  movsd LC(%rip), %xmm0
  minsd %xmm1, %xmm0

becomes:

  minsd LC(%rip), %xmm0

llvm-svn: 162187

llvm-svn: 162186

Reported by: Francisco Lopes  <oblita@gmail.com>

llvm-svn: 162182

llvm-svn: 162181

llvm-svn: 162180

These nodes are no longer needed because the peephole pass can fold
CMOV+AND into ANDCC etc.

llvm-svn: 162179

Remove virtual from many methods. These methods replace methods in the base class, but the base class methods aren't virtual so it just increased call overhead.

llvm-svn: 162178

This turns common i1 patterns into predicated instructions:

  (add (zext cc), x) -> (select cc (add x, 1), x)
  (add (sext cc), x) -> (select cc (add x, -1), x)

For a function like:

  unsigned f(unsigned s, int x) {
    return s + (x>0);
  }

We now produce:

  cmp r1, #0
  it  gt
  addgt.w r0, r0, #1

Instead of:

  movs  r2, #0
  cmp r1, #0
  it  gt
  movgt r2, #1
  add r0, r2

llvm-svn: 162177

Add these transformations to the existing add/sub ones:

  (and (select cc, -1, c), x) -> (select cc, x, (and, x, c))
  (or  (select cc, 0, c), x)  -> (select cc, x, (or, x, c))
  (xor (select cc, 0, c), x)  -> (select cc, x, (xor, x, c))

The selects can then be transformed to a single predicated instruction
by peephole.

This transformation will make it possible to eliminate the ISD::CAND,
COR, and CXOR custom DAG nodes.

llvm-svn: 162176

llvm-svn: 162175

llvm-svn: 162174

SimplifyLibcalls: Add fabs and trunc to the list of libcalls that are safe to shrink from double to float.

llvm-svn: 162173

Reapply r162160 with a fix: Optimize Arith->Trunc->SETCC sequence to allow better compare/branch code.

llvm-svn: 162172

In Debug builds, VerifyDiagnosticConsumer checks any files with diagnostics
to make sure we got the chance to parse them for directives (expected-warning
and friends). This check previously relied on every parsed file having a
FileEntry, which broke the cling interpreter's test suite.

This commit changes the extra debug checking to mark a file as unparsed
as soon as we see a diagnostic from that file. At the very end, any files
that are still marked as unparsed are checked for directives, and a fatal
error is emitted (as before) if we find out that there were directives we
missed. -verify directives should always live in actual parsed files, not
in PCH or AST files.

Patch by Andy Gibbs, with slight modifications by me.

llvm-svn: 162171

Make sure the generic pattern is used.

llvm-svn: 162170

llvm-svn: 162169

llvm-svn: 162168

when you want to find the caller's saved pc, you look up the return address
register and use that.  On arm, for instance, this would be the contents of
the link register (lr).

If the eh_frame CIE defines an RA, record that fact in the UnwindPlan.

When we're finding a saved register, if it's the pc, lok for the location
of the return address register instead.

<rdar://problem/12062310> 

llvm-svn: 162167