llvm-svn: 191838

llvm-svn: 191818

otherwise encoding fails after the last change in X86MCCodeEmitter.cpp.

llvm-svn: 191812

llvm-svn: 191790

llvm-svn: 191789

llvm-svn: 191788

llvm-svn: 191777

There are no corresponding patterns for small immediates because they would
prevent the use of fused compare-and-branch instructions.

llvm-svn: 191775

llvm-svn: 191774

llvm-svn: 191773

This involves using RISB[LH]G, whereas the equivalent z10 optimization
uses RISBG.

llvm-svn: 191770

As the comment says, we always want to use STOC for 32-bit stores.

llvm-svn: 191767

This function-attribute modifies the callee-saved register list and function
epilogue (specifically the return instruction) so that a routine is suitable
for use as an interrupt-handler of the specified type without disrupting
user-mode applications.

rdar://problem/14207019

llvm-svn: 191766

Floats are stored in the high 32 bits of an FPR, and the only GPR<->FPR
transfers are full-register transfers.  This patch optimizes GPR<->FPR
float transfers when the high word of a GPR is directly accessible.

llvm-svn: 191764

llvm-svn: 191762

llvm-svn: 191759

Patch by Alp Toker.

llvm-svn: 191757

llvm-svn: 191755

llvm-svn: 191753

llvm-svn: 191751

Similar to low words, we can use the shorter LLIHL and LLIHH if it turns
out that the other half of the GR64 isn't live.

llvm-svn: 191750

Pointed out by Joerg.

llvm-svn: 191749

llvm-svn: 191748

llvm-svn: 191746

This also removes the restriction on the immediate field of the 'hint'
instruction.

llvm-svn: 191744

llvm-svn: 191743

llvm-svn: 191742

llvm-svn: 191740

This just adds the basics necessary for allocating the upper words to
virtual registers (move, load and store).  The move support is parameterised
in a way that makes it easy to handle zero extensions, but the associated
zero-extend patterns are added by a later patch.

The easiest way of testing this seemed to be add a new "h" register
constraint for high words.  I don't expect the constraint to be useful
in real inline asms, but it should work, so I didn't try to hide it
behind an option.

llvm-svn: 191739

Originally committed as r191661, but reverted because it changed the matching
order of comparisons on some hosts.  That should have been fixed by r191735.

llvm-svn: 191738

llvm-svn: 191737

This patch adds aliases for Mips sub instruction with immediate operands. Corresponding test cases are added.

llvm-svn: 191734

llvm-svn: 191733

llvm-svn: 191732

llvm-svn: 191731

llvm-svn: 191728

llvm-svn: 191715

on ADD16rr opcodes, if src1 != src, since that would cause 
convertToThreeAddress to try to create a virtual register. This is not
permitted after register allocation, which is when the X86FixupLEAs pass
runs.

This patch fixes PR16785.

llvm-svn: 191711

This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b.


Patch by Matheus Almeida

llvm-svn: 191688

This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}.


Patch by Matheus Almeida

llvm-svn: 191687