llvm-svn: 26297

llvm-svn: 26296

Added generic vector types: VR64 and VR128.

llvm-svn: 26295

packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).

llvm-svn: 26294

llvm-svn: 26292

advantage of fisttpll.

llvm-svn: 26288

llvm-svn: 26283

llvm-svn: 26281

llvm-svn: 26278

llvm-svn: 26273

llvm-svn: 26260

llvm-svn: 26259

and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.

llvm-svn: 26255

llvm-svn: 26253

issue. Need to do more experiments.

llvm-svn: 26247

llvm-svn: 26246

llvm-svn: 26245

llvm-svn: 26244

   proves to be worth 20% on Ptrdist/ks. Might be related to dependency
   breaking support.
2. Added FsMOVAPSrr and FsMOVAPDrr as aliases to MOVAPSrr and MOVAPDrr. These
   are used for FR32 / FR64 reg-to-reg copies.
3. Tell reg-allocator to generate MOVSSrm / MOVSDrm and MOVSSmr / MOVSDmr to
   spill / restore FsMOVAPSrr and FsMOVAPDrr.

llvm-svn: 26241

llvm-svn: 26240

and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.

llvm-svn: 26238

llvm-svn: 26234

transfer.

According to the Intel P4 Optimization Manual:

Moves that write a portion of a register can introduce unwanted
dependences. The movsd reg, reg instruction writes only the bottom
64 bits of a register, not to all 128 bits. This introduces a dependence on
the preceding instruction that produces the upper 64 bits (even if those
bits are not longer wanted). The dependence inhibits register renaming,
and thereby reduces parallelism.

Not to mention movaps is shorter than movss.

llvm-svn: 26226

Turns them into calls to memset / memcpy if 1) buffer(s) are not DWORD aligned,
2) size is not known to be greater or equal to some minimum value (currently 128).

llvm-svn: 26224

llvm-svn: 26197

llvm-svn: 26196

llvm-svn: 26193

llvm-svn: 26192

llvm-svn: 26186

llvm-svn: 26183

XMM registers were not being handled.

llvm-svn: 26182

llvm-svn: 26180

llvm-svn: 26179

llvm-svn: 26174

llvm-svn: 26173

maxStoresPerMemMove. Although the last one is not used.

llvm-svn: 26172

llvm-svn: 26169

CALLSEQ_START nodes.

llvm-svn: 26143

X86 addressing mode. Currently we do not allow any node whose target node
produces a chain as well as any node that is at the root of the addressing
mode expression tree.

llvm-svn: 26117

llvm-svn: 26111