llvm-svn: 57368

Extend set of return registers on sparc until someone will implement MRV support there. At least, this will allow libgcc compile, however we are not ABI-compatible with stuff compiled with native gcc.

llvm-svn: 57364

llvm-svn: 57363

llvm-svn: 57362

llvm-svn: 57359

llvm-svn: 57358

llvm-svn: 57346

Add dummy 'm' inline asm constraint handler for Sparc. I'm not sure, whether it is correct, however :)

llvm-svn: 57345

llvm-svn: 57344

Instead, just create one, and make sure everything that needs
it can access it. Previously most of the SelectionDAGISel
subclasses all had their own TargetLowering object, which was
redundant with the TargetLowering object in the TargetMachine
subclasses, except on Sparc, where SparcTargetMachine
didn't have a TargetLowering object. Change Sparc to work
more like the other targets here.

llvm-svn: 57016

isReg, etc., from isRegister, etc.

llvm-svn: 57006

instead of hasWeakLinkage in a bunch of optimization
passes.

llvm-svn: 56782

llvm-svn: 56641

llvm-svn: 56573

llvm-svn: 56572

instruction opcodes are now numbered. No functionality change.

llvm-svn: 56497

default.

llvm-svn: 56471

Apologies for the thrashing.

llvm-svn: 56251

- Add linkage to SymbolSDNode (default to external).
- Change ISD::ExternalSymbol to ISD::Symbol.
- Change ISD::TargetExternalSymbol to ISD::TargetSymbol

These changes pave the way to allowing SymbolSDNodes with non-external linkage.

llvm-svn: 56249

isImmediate(), isRegister(), and friends, to avoid confusion
about having two different names with the same meaning. I'm
not attached to the longer names, and would be ok with
changing to the shorter names if others prefer it.

llvm-svn: 56189

Currently it just holds the calling convention and flags
for isVarArgs and isTailCall.

And it has several utility methods, which eliminate magic
5+2*i and similar index computations in several places.

CallSDNodes are not CSE'd. Teach UpdateNodeOperands to handle
nodes that are not CSE'd gracefully.

llvm-svn: 56183

with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.

llvm-svn: 56159

llvm-svn: 55779

No functional change (and no FE change to generate them).

llvm-svn: 55753

llvm-svn: 55504

was inserted or not.  This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.

llvm-svn: 55375

process up to a higher level. This allows FastISel to leverage
more of SelectionDAGISel's infastructure, such as updating Machine
PHI nodes.

Also, implement transitioning from SDISel back to FastISel in
the middle of a block, so it's now possible to go back and
forth. This allows FastISel to hand individual CallInsts and other
complicated things off to SDISel to handle, while handling the rest
of the block itself.

To help support this, reorganize the SelectionDAG class so that it
is allocated once and reused throughout a function, instead of
being completely reallocated for each block.

llvm-svn: 55219

from all targets.

llvm-svn: 55124

llvm-svn: 55092

llvm-svn: 54844

Reduce heap trashing due to std::string construction / concatenation via caching of section flags string representations

llvm-svn: 54842

Convert uses of std::vector in TargetInstrInfo to SmallVector.  This change had to be propoagated down into all the targets and up into all clients of this API.

llvm-svn: 54802

llvm-svn: 54543

llvm-svn: 54541

llvm-svn: 54540

llvm-svn: 54456

llvm-svn: 54455

llvm-svn: 54450

llvm-svn: 54313

llvm-svn: 54128