Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler.

llvm-svn: 106091

and End arguments by-value rather than by-reference.

llvm-svn: 101830

llvm-svn: 92837

llvm-svn: 90970

Remove some old experimental code that is no longer needed. Remove additional, speculative scheduling pass as its cost did not translate into significant performance improvement. Minor tweaks.

llvm-svn: 89471

llvm-svn: 89404

llvm-svn: 88682

Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies. 

llvm-svn: 86628

Break anti-dependencies using free registers in a round-robin manner to avoid introducing new anti-dependencies.

llvm-svn: 86098

Do a scheduling pass ignoring anti-dependencies to identify candidate registers that should be renamed.

llvm-svn: 85939

llvm-svn: 85522

llvm-svn: 85412

Allow the aggressive anti-dep breaker to process the same region multiple times. This is necessary because new anti-dependencies are exposed when "current" ones are broken.

llvm-svn: 85166

Add aggressive anti-dependence breaker. Currently it is not the default for any target. Enable with -break-anti-dependencies=all.

llvm-svn: 85145