and cases alphabetically.  No functionality change.

llvm-svn: 75001

these instructions, no autoupgrade or backwards compatibility support is
provided.

llvm-svn: 74991

llvm-svn: 74985

VSETCC must define all bits, which is different than it was documented
to before.  Since all targets that implement VSETCC already have this
behavior, and we don't optimize based on this, just change the 
documentation.  We now get nice code for vec_compare.ll

llvm-svn: 74978

for now, conservatively return false.

llvm-svn: 74969

as "X" constraint and "P" modifier on x86.  Make this work.
(Change may not be sufficient to fix it for non-Darwin, but
I'm pretty sure it won't break anything.)
gcc.apple/asm-block-32.c
gcc.apple/asm-block-33.c

llvm-svn: 74967

the input is legal (4 x i32)

llvm-svn: 74964

llvm-svn: 74962

finishes off enough support for vector compares to get the icmp/fcmp
version of 2008-07-23-VSetCC.ll passing.

llvm-svn: 74961

(vector of bool).

llvm-svn: 74960

eliminate the former.

llvm-svn: 74959

llvm-svn: 74957

llvm-svn: 74953

llvm-svn: 74949

llvm-svn: 74931

llvm-svn: 74925

 previous cmp; a copy can not be inserted here if the copy insn also has
 side effects. We don't have access to the attributes of copy insn here;
 so just play safe by finding a safe locations for branch terminators.

llvm-svn: 74898

llvm-svn: 74857

llvm-svn: 74825

llvm-svn: 74821

Cleanup MachO writer and code emitter. Fix 80 cols problems, remove extra spaces, shrink down includes and move some methods out-of-line

llvm-svn: 74817

llvm-svn: 74814

cleanup, removed some #includes and moved Object Code Emitter out-of-line.

llvm-svn: 74813

llvm-svn: 74807

Add NumFixedArgs attribute to CallSDNode which indicates the number of fixed arguments in a vararg call.

With the SVR4 ABI on PowerPC, vector arguments for vararg calls are passed differently depending on whether they are a fixed or a variable argument. Variable vector arguments always go into memory, fixed vector arguments are put 
into vector registers. If there are no free vector registers available, fixed vector arguments are put on the stack.

The NumFixedArgs attribute allows to decide for an argument in a vararg call whether it belongs to the fixed or variable portion of the parameter list.

llvm-svn: 74764

llvm-svn: 74760

llvm-svn: 74733

llvm-svn: 74720

llvm-svn: 74718

llvm-svn: 74686

llvm-svn: 74677

llvm-svn: 74673

llvm-svn: 74659

llvm-svn: 74625

CommuteChangesDestination() should check if to-be-commuted instruction defines any register. Also teaches the default commuteInstruction() to commute instruction without definitions (e.g. X86::test / ARM::tsp).

llvm-svn: 74602

Remove special handling of implicit_def. Fix a couple more bugs in liveintervalanalysis and coalescer handling of implicit_def.

Note, isUndef marker must be placed even on implicit_def def operand or else the scavenger will not ignore it. This is necessary because -O0 path does not use liveintervalanalysis, it treats implicit_def just like any other def.

llvm-svn: 74601

Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details.

llvm-svn: 74580

 - This more or less amounts to a revert of r65379. I'm curious to know what
   happened that caused this variable to become unused.

llvm-svn: 74579

have the alignment be calculated up front, and have the back-ends obey whatever
alignment is decided upon.

This allows for future work that would allow for precise no-op placement and the
like.

llvm-svn: 74564

Temporarily restore the scavenger implicit_def checking code. MachineOperand isUndef mark is not being put on implicit_def of physical registers (created for parameter passing, etc.).

llvm-svn: 74519