Commits · d6d5a2571fa4c0d11eea08674b0ad81cfc9b8498 · Roger Ferrer / llvm-epi-0.8 · GitLab

This project is archived. Its data is read-only.

Jan 30, 2018
- [AMDGPU] Add options for waitcnt pass debugging; add instr count in debug output. · d6d5a257
  Mark Searles authored Jan 30, 2018
  d6d5a257
- AMDGPU/SI: Add decoding in the GFX80_UNPACKED decoding namespace. · 0905870f
  Changpeng Fang authored Jan 30, 2018
  0905870f
- [AArch64] Add new target feature to fuse address generation with load or store · f1d01645
  Evandro Menezes authored Jan 30, 2018
  f1d01645
- [mips] Fix incorrect sign extension for fpowi libcall · daaeaba6
  Simon Dardis authored Jan 30, 2018
  daaeaba6
- Re-commit : [PowerPC] Add handling for ColdCC calling convention and a pass to mark · 1f59ae31
  Zaara Syeda authored Jan 30, 2018
  1f59ae31
- [AArch64] Add new target feature to handle cheap as move for Exynos · 07c78eee
  Evandro Menezes authored Jan 30, 2018
  07c78eee
- [AArch64] Add pipeline model for Exynos M3 · 9f9daa1f
  Evandro Menezes authored Jan 30, 2018
  9f9daa1f
- Revert "[X86] Avoid using high register trick for test instruction" · 0b69b5ed
  Eric Liu authored Jan 30, 2018
  0b69b5ed
- Spelling mistake in comment. NFCI. · eb070161
  Simon Pilgrim authored Jan 30, 2018
  eb070161
- [ARM GlobalISel] Map G_SITOFP and G_UITOFP · 2a5b9620
  Diana Picus authored Jan 30, 2018
  2a5b9620
- [ARM GlobalISel] Legalize G_SITOFP and G_UITOFP · 517531e5
  Diana Picus authored Jan 30, 2018
  517531e5
- [ARM GlobalISel] Map G_FPTOSI and G_FPTOUI · a2da0302
  Diana Picus authored Jan 30, 2018
  a2da0302
- [ARM GlobalISel] Legalize G_FPTOSI and G_FPTOUI · 4ed0ee7b
  Diana Picus authored Jan 30, 2018
  4ed0ee7b
- AMDGPU: Move ADDRIndirect complex pattern into R600Instructions.td · 3ae38d27
  Tom Stellard authored Jan 29, 2018
  3ae38d27
- [X86] Use VMOVDQA64 for aligned vXi32 stores. · 571231a7
  Craig Topper authored Jan 29, 2018
  571231a7
- AMDGPU: Allow a SGPR for the conditional KILL operand · 48057b55
  Marek Olsak authored Jan 29, 2018
  48057b55
Jan 29, 2018
- [X86] Add FeaturePOPCNTFalseDeps to skylake server CPU to match skylake client. · a8f87a36
  Craig Topper authored Jan 29, 2018
  a8f87a36
- [X86] Emit 11-byte or 15-byte NOPs on recent AMD targets, else default to 10-byte NOPs (PR22965) · 02bdac53
  Simon Pilgrim authored Jan 29, 2018
  02bdac53
- [ARM][GISel] PR35965 Constrain RegClasses of nested instructions built from Dst Pattern · 08464524
  Daniel Sanders authored Jan 29, 2018
  08464524
- [X86] Avoid using high register trick for test instruction · 015184b7
  Amaury Sechet authored Jan 29, 2018
  015184b7
- [AArch64] Change the filename of the Exynos M1 scheduling defs · 1589d6e6
  Evandro Menezes authored Jan 29, 2018
  1589d6e6
- Revert "AArch64: Omit callframe setup/destroy when not necessary" · fc7d56d9
  Jun Bum Lim authored Jan 29, 2018
  fc7d56d9
- [globalisel][legalizer] Adapt LegalizerInfo to support inter-type dependencies and other things. · 79cb839f
  Daniel Sanders authored Jan 29, 2018
  79cb839f
- [AMDGPU][X86][Mips] Make sure renamable bit not set for reserved regs · d37dc77b
  Geoff Berry authored Jan 29, 2018
  d37dc77b
- [X86] Don't create SHRUNKBLEND when the condition is used by the true or false... · eb13ebdb
  Craig Topper authored Jan 29, 2018
  eb13ebdb
- [globalisel] Make LegalizerInfo::LegalizeAction available outside of LegalizerInfo. NFC · 9ade5592
  Daniel Sanders authored Jan 29, 2018
  9ade5592
- [AMDGPU][MC] Corrected parsing of image opcode modifiers r128 and d16 · 4f321aef
  Dmitry Preobrazhensky authored Jan 29, 2018
  4f321aef
- [AArch64][AsmParser] NFC: Generalize LogicalImm[Not](32|64) code · a1c259c2
  Sander de Smalen authored Jan 29, 2018
  a1c259c2
- [Sparc] Account for bias in stack readjustment · 865de57b
  Jonas Devlieghere authored Jan 29, 2018
  865de57b
- [ARM] FP16Pat and FullFP16Pat patterns. NFC. · 3ddb7fb6
  Sjoerd Meijer authored Jan 29, 2018
  3ddb7fb6
- [X86FixupBWInsts] Fix miscompilation if sibling sub-register is live. · c560a18c
  Andrei Elovikov authored Jan 29, 2018
  c560a18c
- [AArch64] Generate the CASP instruction for 128-bit cmpxchg · a9d2e004
  Oliver Stannard authored Jan 29, 2018
  a9d2e004
- [NFC] fix trivial typos in comments and documents · c8e92458
  Hiroshi Inoue authored Jan 29, 2018
  c8e92458
Jan 28, 2018
- [X86] Fix a crash that can occur in combineExtractVectorElt due to not... · 3913a4dd
  Craig Topper authored Jan 28, 2018
  3913a4dd
- [X86] Remove VPTESTM/VPTESTNM ISD opcodes. Use isel patterns matching cmpm eq/ne with immallzeros. · 15d69739
  Craig Topper authored Jan 28, 2018
  15d69739
- [X86] Add patterns for using masked vptestnmd for 256-bit vectors without VLX. · 5e4b4536
  Craig Topper authored Jan 27, 2018
  5e4b4536
Jan 27, 2018
- [X86] Use vptestm/vptestnm for comparisons with zero to avoid creating a zero vector. · 247016a7
  Craig Topper authored Jan 27, 2018
  247016a7
- [X86] Remove X86ISD::PCMPGTM/PCMPEQM and instead just use X86ISD::PCMPM and... · 513d3fa6
  Craig Topper authored Jan 27, 2018
  513d3fa6
- [X86][SSE] Simplify demanded elements from BROADCAST shuffle source. · fe3fac80
  Simon Pilgrim authored Jan 27, 2018
  fe3fac80
Jan 26, 2018
- [X86] Use vpternlog to implement vector not under AVX512. · 8a444ee6
  Craig Topper authored Jan 26, 2018
  8a444ee6