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  11. Apr 30, 2008
    • Arnold Schwaighofer's avatar
      Tail call optimization improvements: · be0de34e
      Arnold Schwaighofer authored
      Move platform independent code (lowering of possibly overwritten
      arguments, check for tail call optimization eligibility) from
      target X86ISelectionLowering.cpp to TargetLowering.h and
      SelectionDAGISel.cpp.
      
      Initial PowerPC tail call implementation:
      
      Support ppc32 implemented and tested (passes my tests and
      test-suite llvm-test).  
      Support ppc64 implemented and half tested (passes my tests).
      On ppc tail call optimization is performed if 
        caller and callee are fastcc
        call is a tail call (in tail call position, call followed by ret)
        no variable argument lists or byval arguments
        option -tailcallopt is enabled
      Supported:
       * non pic tail calls on linux/darwin
       * module-local tail calls on linux(PIC/GOT)/darwin(PIC)
       * inter-module tail calls on darwin(PIC)
      If constraints are not met a normal call will be emitted.
      
      A test checking the argument lowering behaviour on x86-64 was added.
      
      llvm-svn: 50477
      be0de34e
    • Dale Johannesen's avatar
      Add comments for previous patch as requested. · c110c4a5
      Dale Johannesen authored
      llvm-svn: 50463
      c110c4a5
    • Scott Michel's avatar
      Fix custom target lowering for zero/any/sign_extend: make sure that · be940424
      Scott Michel authored
      DAG.UpdateNodeOperands() is called before (not after) the call to
      TLI.LowerOperation().
      
      llvm-svn: 50461
      be940424
    • Dale Johannesen's avatar
      Make eh_frame objects by 8-byte aligned on 64-bit · fc3e3ad7
      Dale Johannesen authored
      targets.
      
      llvm-svn: 50451
      fc3e3ad7
  12. Apr 29, 2008
    • Roman Levenstein's avatar
      Use std::set instead of std::priority_queue for the RegReductionPriorityQueue. · 6b371145
      Roman Levenstein authored
      This removes the existing bottleneck related to the removal of elements from 
      the middle of the queue.
      
      Also fixes a subtle bug in ScheduleDAGRRList::CapturePred:
      It was updating the state of the SUnit before removing it. As a result, the
      comparison operators were working incorrectly and this SUnit could not be removed 
      from the queue properly.
      
      Reviewed by Evan and Dan. Approved by Dan.
      
      llvm-svn: 50412
      6b371145
    • Chris Lattner's avatar
      make the vector conversion magic handle multiple results. · 5c88f7b1
      Chris Lattner authored
      We now compile test2/test3 to:
      
      _test2:
      	## InlineAsm Start
      	set %xmm0, %xmm1
      	## InlineAsm End
      	addps	%xmm1, %xmm0
      	ret
      _test3:
      	## InlineAsm Start
      	set %xmm0, %xmm1
      	## InlineAsm End
      	paddd	%xmm1, %xmm0
      	ret
      
      as expected.
      
      llvm-svn: 50389
      5c88f7b1
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