llvm-svn: 96343

not the end of the field, fixing rdar://7651978

llvm-svn: 96330

llvm-svn: 96289

llvm-svn: 96288

Preliminary patch to improve dwarf EH generation - Hooks to return Personality / FDE / LSDA / TType encoding depending on target / options (e.g. code model / relocation model) - MCIzation of Dwarf EH printer to use encoding information - Stub generation for ELF target (needed for indirect references) - Some other small changes here and there

llvm-svn: 96285

and the testcase needs improvement.

llvm-svn: 96265

IsLegalToFold and IsProfitableToFold. The generic version of the later simply checks whether the folding candidate has a single use.

This allows the target isel routines more flexibility in deciding whether folding makes sense. The specific case we are interested in is folding constant pool loads with multiple uses.

llvm-svn: 96255

Add support for emitting non-temporal stores for DAGs marked
non-temporal.

llvm-svn: 96241

Remove an assumption of default arguments.  This is in anticipation of a
change to SelectionDAG build APIs.

llvm-svn: 96239

Remove an assumption of default arguments.  This is in anticipation of a
change to SelectionDAG build APIs.

llvm-svn: 96228

isInteger, we now have isFloatTy and isIntegerTy.  Requested by Chris!

llvm-svn: 96223

llvm-svn: 96174

Otherwise AT&T asm printer is used with non-compatible MCAsmInfo and
there is no way to override this behaviour.

llvm-svn: 96165

encoding them into nothing.

llvm-svn: 96110

llvm-svn: 96088

llvm-svn: 96076

tables.

llvm-svn: 96073

created. This ensures it's updated at all time. It means targets which perform
dynamic stack alignment would know whether it is required and whether frame
pointer register cannot be made available register allocation.
This is a fix for rdar://7625239. Sorry, I can't create a reasonably sized test
case.

llvm-svn: 96069

llvm-svn: 96065

We still have the templated X86 JIT emitter, *and* the
almost-copy in X86InstrInfo for getting instruction sizes.

llvm-svn: 96059

fix swapgs to be spelled right.

llvm-svn: 96058

llvm-svn: 96055

encoder and decoder by using new MRM_ forms.

llvm-svn: 96048

rip-relative addresses, and add a testcase.

llvm-svn: 96040

llvm-svn: 96038

addressing.  This isn't complete because I need an MCContext
to generate new MCExprs.

llvm-svn: 96036

llvm-svn: 96031

llvm-svn: 96029

llvm-svn: 96028

is pc relative or not, mark call and branches as pcrel.

llvm-svn: 96026

llvm-svn: 96011

llvm-svn: 95981

This should fix alot of problems we saw so far, e.g. PRs 5851 & 2936

llvm-svn: 95980

This will work better for the disassembler for modeling things
like lfence/monitor/vmcall etc.

llvm-svn: 95960

great solution for the disassembler, we'll go with "plan b".

llvm-svn: 95957

with "tied memory operands", which is wrong.

llvm-svn: 95950

llvm-svn: 95949

movq	(%ecx,%edx,2), %xmm2
movhps	(%ecx,%eax,2), %xmm2

rather than:

movq     (%eax, %edx, 2), %xmm2		
movq     (%eax, %ebx, 2), %xmm3		
movlhps  %xmm3, %xmm2			

Testcase forthcoming.

llvm-svn: 95948

busted in both encoders.  I'm not bothering to fix it in the
old one at this point.

llvm-svn: 95947

	testb	%al, %al                ## <MCInst #2412 TEST8rr
                                        ##   <MCOperand Reg:2>
                                        ##   <MCOperand Reg:2>>
	jne	LBB1_7                  ## <MCInst #938 JNE_1
                                        ##   <MCOperand Expr:(LBB1_7)>>

llvm-svn: 95935