LiveIntervals::Interval::expiredAt() and simplify regalloc code.

llvm-svn: 10894

llvm-svn: 10893

when we join intervals and one of the two will need to be removed.

llvm-svn: 10892

llvm-svn: 10847

LiveIntervals::Interval::liveAt. Both were considering the live ranges
closed in the end, when they are actually open.

llvm-svn: 10835

llvm-svn: 10834

be dead at the defining instruction but can only be killed in
subsequent ones.

llvm-svn: 10833

LiveVariables.

llvm-svn: 10830

llvm-svn: 10824

ranges, i.e. [a,b)

llvm-svn: 10822

of a physical register is always dominated by a def).

llvm-svn: 10821

llvm-svn: 10820

overlap before adding their spill weight.

llvm-svn: 10819

when an implicitely defined register is later used by an alias. For example:

         call foo
         %reg1024 = mov %AL

The call implicitely defines EAX but only AL is used. Before this fix
no information was available on AL. Now EAX and all its aliases except
AL get defined and die at the call instruction whereas AL lives to be
killed by the assignment.

llvm-svn: 10813

LiveVariables::HandlePhysRegDef private they use information that is
not in memory when LiveVariables finishes the analysis.

Also update the TwoAddressInstructionPass to not use this interface.

llvm-svn: 10755

llvm-svn: 10749

This should get hunked over to the Sparc backend, along with
MachineCodeForInstruction and a bunch of files in include/llvm/Codegen,
but those battles will have to wait for a later time.

llvm-svn: 10731

llvm-svn: 10730

llvm-svn: 10728

of the register allocator as follows:

       before   after
mesa   2.3790  1.5994
vpr    2.6008  1.2078
gcc    1.9840  0.5273
mcf    0.2569  0.0470
eon    1.8468  1.4359
twolf  0.9475  0.2004
burg   1.6807  1.3300
lambda 1.2191  0.3764

Speedups range anyware from 30% to over 400% :-)

llvm-svn: 10712

llvm-svn: 10711

llvm-svn: 10710

30-50% decrease in running time of the linear scan register allocator.

llvm-svn: 10707

llvm-svn: 10695

llvm-svn: 10692

A = B op C where A == C, but this cannot really occur in practice
because of SSA form. Add an assert to check that just to be safe.

llvm-svn: 10682

llvm-svn: 10681

implementation from the TargetMachine directly.

llvm-svn: 10636

saved register it has a longer free range than ECX (which is defined
every time there is a fnuction call) which makes ECX a better register
to reserve.

llvm-svn: 10635

which denotes the register we would like to be assigned to (virtual or
physical). In register allocation, if this hint exists and we can map
it to a physical register (it is either a physical register or it is a
virtual register that already got assigned to a physical one) we use
that register if it is available instead of a random one in the free
pool.

llvm-svn: 10634

llvm-svn: 10632

llvm-svn: 10626

llvm-svn: 10623

llvm-svn: 10621

minor cleanups

llvm-svn: 10619

llvm-svn: 10604

with live intervals was missing registers that were used before they
were defined (in the arbitrary order live intervals numbers
instructions).

llvm-svn: 10603

allocation in the presence of preallocated intervals.

llvm-svn: 10595

llvm-svn: 10584

llvm-svn: 10570