void test6() {
  Y = 0xABCD0123BCDE4567;
}

into:

_test6:
        lis r2, -21555
        lis r3, ha16(_Y)
        ori r2, r2, 291
        rldicr r2, r2, 32, 31
        oris r2, r2, 48350
        ori r2, r2, 17767
        std r2, lo16(_Y)(r3)
        blr

llvm-svn: 28885

set, so disable the pattern in that case.

llvm-svn: 28884

Split imm16Shifted into a sext/zext form for 64-bit support.
Add some patterns for immediate formation.  For example, we now compile this:

static unsigned long long Y;
void test3() {
  Y = 0xF0F00F00;
}

into:

_test3:
        li r2, 3840
        lis r3, ha16(_Y)
        xoris r2, r2, 61680
        std r2, lo16(_Y)(r3)
        blr

GCC produces:

_test3:
        li r0,0
        lis r2,ha16(_Y)
        ori r0,r0,61680
        sldi r0,r0,16
        ori r0,r0,3840
        std r0,lo16(_Y)(r2)
        blr

llvm-svn: 28883

llvm-svn: 28881

llvm-svn: 28880

static unsigned long long X, Y;
void test1() {
  X = Y;
}

into:

_test1:
        lis r2, ha16(_Y)
        lis r3, ha16(_X)
        ld r2, lo16(_Y)(r2)
        std r2, lo16(_X)(r3)
        blr

llvm-svn: 28879

removed, tblgen produces identical output to with them in.

llvm-svn: 28867

llvm-svn: 28866

llvm-svn: 28864

llvm-svn: 28862

llvm-svn: 28860

fixes test/Regression/CodeGen/ARM/ret_arg5.ll

llvm-svn: 28854

llvm-svn: 28848

magic to work.

llvm-svn: 28847

llvm-svn: 28843

llvm-svn: 28841

llvm-svn: 28840

now compile:

static unsigned long X;
void test1() {
  X = 0;
}

into:

_test1:
        lis r2, ha16(_X)
        li r3, 0
        stw r3, lo16(_X)(r2)
        blr

Totally amazing :)

llvm-svn: 28839

llvm-svn: 28838

llvm-svn: 28837

the target triple & subtarget info.  woo.

llvm-svn: 28835

Remove explicit casts to std::string now that there is no overload resolution
issues in the TargetData ctors.

llvm-svn: 28830

add a new init method.

llvm-svn: 28828

support, and 64-bit register use are all consistent with each other.

Add a new "IsPPC" feature, to distinguish ppc32 vs ppc64 targets, use this
to configure TargetData differently.  This not makes ppc64 blow up on lots
of stuff :)

llvm-svn: 28825

can in 32-bit mode we can choose to optionally *use* 64-bit registers.

llvm-svn: 28824

that is currently just like ppc32 :)

llvm-svn: 28813

llvm-svn: 28808

2. Add vector support.

llvm-svn: 28807

llvm-svn: 28798

llvm-svn: 28797

llvm-svn: 28796

vector types are passed via XMM registers.

llvm-svn: 28789

llvm-svn: 28787

llvm-svn: 28783

functions.

llvm-svn: 28781

llvm-svn: 28772

llvm-svn: 28769

ComputeMaskedBits.  DemandedMasks and KnownZero/One masks should never have
bits set out of the range of the base datatype.

llvm-svn: 28768

llvm-svn: 28765

llvm-svn: 28764