llvm-svn: 40672

llvm-svn: 40658

mnemonics from their operands instead of single spaces. This makes the
assembly output a little more consistent with various other compilers
(f.e. GCC), and slightly easier to read. Also, update the regression
tests accordingly.

llvm-svn: 40648

Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v4f32 s2v (f32 load ))), 0) -> (i32 load )

llvm-svn: 40628

llvm-svn: 40617

llvm-svn: 40594

it does not have a Module parameter.

llvm-svn: 40590

llvm-svn: 40589

llvm-svn: 40586

Change the x86 backend to use extract_subreg for truncation operations. Passes DejaGnu, SingleSource and MultiSource.

llvm-svn: 40578

llvm-svn: 40572

llvm-svn: 40566

Make the alignedload and alignedstore patterns always require 16-byte
alignment. This way when they are used in the "Fs" instructions, in which
a vector instruction is used for a scalar purpose, they can still require
the full vector alignment. And add a regression test for this.

llvm-svn: 40555

still under discussion.

llvm-svn: 40549

llvm-svn: 40547

llvm-svn: 40538

llvm-svn: 40537

llvm-svn: 40535

don't get decorated as if for immediate fields for instructions.

llvm-svn: 40529

llvm-svn: 40528

llvm-svn: 40518

llvm-svn: 40517

llvm-svn: 40516

x86 target, replacing them with the new alignment attributes on memory
references.

llvm-svn: 40504

llvm-svn: 40502

llvm-svn: 40501

llvm-svn: 40499

AsmPrinter::doFinalization.

llvm-svn: 40487

llvm-svn: 40483

 - Split EH and debug infiormation
 - Make DwarfWriter more verbose in some cases

llvm-svn: 40481

llvm-svn: 40480

register instead of loading each element individually.

llvm-svn: 40478

Pretty hackish, but code itself is dirty mess, so we won't make anything worse. :)

llvm-svn: 40472

llvm-svn: 40443

llvm-svn: 40441

    __builtin_ia32_cvtss2si64
    __builtin_ia32_cvttss2si64
    __builtin_ia32_cvtsi642ss
    __builtin_ia32_cvtsd2si64
    __builtin_ia32_cvttsd2si64
    __builtin_ia32_cvtsi642sd

llvm-svn: 40411

llvm-svn: 40132

llvm-svn: 40123

code that cross integer / floating point domains (e.g. generate pxor / pand for
logical ops on floating point value, movdqa to load / store floating point SSE
values). Given that, it's better to use movaps instead of movdqa and movups
instead of movdqu. They have the same latency but the "aps" variants are one
byte shorter.
If the domain crossing problem is a real performance issue, then we will have to
fix it with dynamic programming based isel.

llvm-svn: 40076

llvm-svn: 40074