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  1. Aug 10, 2009
  2. Aug 06, 2009
  3. Aug 05, 2009
    • Dan Gohman's avatar
      Major calling convention code refactoring. · f9bbcd1a
      Dan Gohman authored
      Instead of awkwardly encoding calling-convention information with ISD::CALL,
      ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
      provides three virtual functions for targets to override:
      LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
      lowering done on the special nodes. They provide the same information, but
      in a more immediately usable format.
      
      This also reworks much of the target-independent tail call logic. The
      decision of whether or not to perform a tail call is now cleanly split
      between target-independent portions, and the target dependent portion
      in IsEligibleForTailCallOptimization.
      
      This also synchronizes all in-tree targets, to help enable future
      refactoring and feature work.
      
      llvm-svn: 78142
      f9bbcd1a
  4. Aug 03, 2009
  5. Aug 01, 2009
  6. Jul 31, 2009
  7. Jul 30, 2009
    • Dan Gohman's avatar
      Rename GRAD to GR32_AD, to follow the naming convention of other · 013f0077
      Dan Gohman authored
      classes. And define its SubRegClassList.
      
      llvm-svn: 77601
      013f0077
    • Evan Cheng's avatar
      Optimize some common usage patterns of atomic built-ins __sync_add_and_fetch()... · e62288fd
      Evan Cheng authored
      Optimize some common usage patterns of atomic built-ins __sync_add_and_fetch() and __sync_sub_and_fetch. 
      
      When the return value is not used (i.e. only care about the value in the memory), x86 does not have to use add to implement these. Instead, it can use add, sub, inc, dec instructions with the "lock" prefix.
      
      This is currently implemented using a bit of instruction selection trick. The issue is the target independent pattern produces one output and a chain and we want to map it into one that just output a chain. The current trick is to select it into a merge_values with the first definition being an implicit_def. The proper solution is to add new ISD opcodes for the no-output variant. DAG combiner can then transform the node before it gets to target node selection.
      
      Problem #2 is we are adding a whole bunch of x86 atomic instructions when in fact these instructions are identical to the non-lock versions. We need a way to add target specific information to target nodes and have this information carried over to machine instructions. Asm printer (or JIT) can use this information to add the "lock" prefix.
      
      llvm-svn: 77582
      e62288fd
  8. Jul 29, 2009
  9. Jul 28, 2009
    • Owen Anderson's avatar
      Return ConstantVector to 2.5 API. · 4aa3295a
      Owen Anderson authored
      llvm-svn: 77366
      4aa3295a
    • Chris Lattner's avatar
      the apple "ld_classic" linker doesn't support .literal16 in 32-bit · a3242e93
      Chris Lattner authored
      mode, and "ld64" (the default linker) falls back to it in -static
      mode.
      
      llvm-svn: 77334
      a3242e93
    • Chris Lattner's avatar
      Rip all of the global variable lowering logic out of TargetAsmInfo. Since · 5e693ed0
      Chris Lattner authored
      it is highly specific to the object file that will be generated in the end,
      this introduces a new TargetLoweringObjectFile interface that is implemented
      for each of ELF/MachO/COFF/Alpha/PIC16 and XCore.
      
      Though still is still a brutal and ugly refactoring, this is a major step
      towards goodness.
      
      This patch also:
      1. fixes a bunch of dangling pointer problems in the PIC16 backend.
      2. disables the TargetLowering copy ctor which PIC16 was accidentally using.
      3. gets us closer to xcore having its own crazy target section flags and
         pic16 not having to shadow sections with its own objects.
      4. fixes wierdness where ELF targets would set CStringSection but not
         CStringSection_.  Factor the code better.
      5. fixes some bugs in string lowering on ELF targets.
      
      llvm-svn: 77294
      5e693ed0
  10. Jul 27, 2009
  11. Jul 25, 2009
  12. Jul 24, 2009
  13. Jul 22, 2009
  14. Jul 21, 2009
  15. Jul 20, 2009
  16. Jul 18, 2009
  17. Jul 15, 2009
  18. Jul 14, 2009
  19. Jul 11, 2009
    • Chris Lattner's avatar
      Fix PR4533, which is about buggy codegen in x86-64 -static mode. · e9190009
      Chris Lattner authored
      Basically, using:
        lea symbol(%rip), %rax
      
      is not valid in -static mode, because the current RIP may not be
      within 32-bits of "symbol" when an app is built partially pic and
      partially static.  The fix for this is to compile it to:
      
        lea symbol, %rax
      
      It would be better to codegen this as:
      
        movq $symbol, %rax
      
      but that will come next.
      
      
      The hard part of fixing this bug was fixing abi-isel, which was actively
      testing for the wrong behavior.  Also, the RUN lines are completely impossible
      to understand what they are testing.  To help with this, convert the -static 
      x86-64 codegen tests to use filecheck.  This is much more stable and makes it
      more clear what the codegen is expected to be.
      
      llvm-svn: 75382
      e9190009
    • Torok Edwin's avatar
      assert(0) -> LLVM_UNREACHABLE. · 56d06597
      Torok Edwin authored
      Make llvm_unreachable take an optional string, thus moving the cerr<< out of
      line.
      LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
      NDEBUG builds.
      
      llvm-svn: 75379
      56d06597
  20. Jul 10, 2009
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