TableGen infers unmodeled side effects on instructions without a
pattern.  Fix some instruction definitions where that was overlooked.

Also raise an error if a rematerializable instruction has unmodeled side
effects. That doen't make any sense.

llvm-svn: 141929

TableGen will mark any pattern-less instruction as having unmodeled side
effects. This is extra bad for V_SET0 which gets rematerialized a lot.

This was part of the cause for PR11125, but the real bug was fixed
in r141923.

llvm-svn: 141924

llvm-svn: 141914

llvm-svn: 141912

llvm-svn: 141909

llvm-svn: 141903

llvm-svn: 141874

Not having it confused assembly printing of jumptables.

llvm-svn: 141862

release the stack segment and reset the stack pointer. Place the code in its own
MBB to make the verifier happy.

llvm-svn: 141859

http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101

--- Reverse-merging r141854 into '.':
U    test/MC/Disassembler/X86/x86-32.txt
U    test/MC/Disassembler/X86/simple-tests.txt
D    test/CodeGen/X86/bmi.ll
U    lib/Target/X86/X86InstrInfo.td
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86.td
U    lib/Target/X86/X86Subtarget.h

llvm-svn: 141857

Should not add instructions to a BB after a return instruction. The machine instruction verifier doesn't like this, nor do I.

llvm-svn: 141856

Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.

llvm-svn: 141854

llvm-svn: 141853

The disassembler needs to use the AM5 factory methods instead of just
building up the immediate directly.

llvm-svn: 141819

llvm-svn: 141811

llvm-svn: 141794

llvm-svn: 141786

llvm-svn: 141781

llvm-svn: 141780

llvm-svn: 141761

Remove unused classes.

llvm-svn: 141757

llvm-svn: 141749

When widening a copy, we are reading a larger register that may not be
live.  Use an <undef> flag to tell the register scavenger and machine
code verifier that we know the value isn't defined.

We now widen:

  %S6<def> = COPY %S4<kill>, %D3<imp-def>

into:

  %D3<def> = VMOVD %D2<undef>, pred:14, pred:%noreg, %S4<imp-use,kill>

This also keeps the <kill> flag on %S4 so we don't inadvertently kill a
live value in %S5.

Finally, ensure that ARMBaseInstrInfo::setExecutionDomain() preserves
the <undef> flag when converting VMOVD to VORR.

llvm-svn: 141746

llvm-svn: 141743

instructions with two register operands derive from it.

llvm-svn: 141742

llvm-svn: 141737

arithmetic and logical instructions with three register operands derive from
them. Fix instruction encoding too.

llvm-svn: 141736

llvm-svn: 141722

Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.

llvm-svn: 141721

llvm-svn: 141720

the real instructions.

llvm-svn: 141718

llvm-svn: 141716

llvm-svn: 141715

llvm-svn: 141708

We parse at least some forms of the instructions now. Encoding is
pretty screwed up, still, though.

llvm-svn: 141704

llvm-svn: 141696

llvm-svn: 141695

llvm-svn: 141694

llvm-svn: 141682

llvm-svn: 141671