memory barrier instructions by definition have side effects. This prevents the post-RA scheduler from moving them around.

llvm-svn: 91150

llvm-svn: 91143

llvm-svn: 91140

llvm-svn: 91090

llvm-svn: 91053

Add memory barrier intrinsic support for ARM. Moving towards adding the atomic operations intrinsics.

llvm-svn: 91003

- Also support the 'q' NEON registers asm code.

llvm-svn: 90894

in "bic sp, sp, #15" leads to unpredicatble behaviour in Thumb2 mode.
Emit the following code instead:
mov r4, sp
bic r4, r4, #15
mov sp, r4

llvm-svn: 90724

MachineBasicBlock::canFallThrough(), which is target-independent and more
thorough.

llvm-svn: 90634

llvm-svn: 90490

llvm-svn: 90419

both source operands.  In the canonical form, the 2nd operand is changed to an
undef and the shuffle mask is adjusted to only reference elements from the 1st
operand.  Radar 7434842.

llvm-svn: 90417

Patch by Howard Hinnant!

llvm-svn: 90365

No functionality change.

llvm-svn: 90336

llvm-svn: 90246

llvm-svn: 90243

For VMOVv*i[16,32], op bit is don't care, and some cmode bits vary depending on
the immediate values.

Ref: Table A7-15 Modified immediate values for Advanced SIMD instructions.
llvm-svn: 90173

for all the processors where I have tried it, and even when it might not help
performance, the cost is quite low.  The opportunities for duplicating
indirect branches are limited by other factors so code size does not change
much due to tail duplicating indirect branches aggressively.

llvm-svn: 90144

llvm-svn: 90141

Make tail duplication of indirect branches much more aggressive (for targets
that indicate that it is profitable), based on further experience with
this transformation.  I compiled 3 large applications with and without
this more aggressive tail duplication and measured minimal changes in code
size.  ("size" on Darwin seems to round the text size up to the nearest
page boundary, so I can only say that any code size increase was less than
one 4k page.) Radar 7421267.

llvm-svn: 89814

llvm-svn: 89748

llvm-svn: 89723

than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.

This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).

llvm-svn: 89720

llvm-svn: 89718

way for each TargetJITInfo subclass to allocate its own stubs. This
means stubs aren't as exactly-sized anymore, but it lets us get rid of
TargetJITInfo::emitFunctionStubAtAddr(), which lets ARM and PPC
support the eager JIT, fixing http://llvm.org/PR4816.

* Rename the JITEmitter's stub creation functions to describe the kind
of stub they create. So far, all of them create lazy-compilation
stubs, but they sometimes get used when far-call stubs are needed.
Fixing http://llvm.org/PR5201 will involve fixing this.

llvm-svn: 89715

Note that "hasDotLocAndDotFile"-style debug info was already broken;
people wanting this functionality should implement it in the
AsmPrinter/DwarfWriter code.

llvm-svn: 89711

It's probably better in the long run to replace the
indirect-GlobalVariable system. That'll be done after a subsequent
patch.

llvm-svn: 89708

Massive refactoring of NEON instructions. Separate opcode from data size specifier suffix, move \t up stream to instruction format, and fix more 80 column violations.
This fixes the NEON asm printing so the "predicate" field is printed between the opcode and the data type suffix.

llvm-svn: 89706

llvm-svn: 89700

VDUPLND and VDUPLNQ to derive from N2V instead of N2VDup.  VDUPLND and VDUPLNQ
now expect op19_18 and op17_16 as the first two args.

llvm-svn: 89699

fold immediate of a + Const into the user as a subtract if it can fit as a negated two-part immediate.

llvm-svn: 89694

{?,?,?,?} as op11_8 for VEXTd and VEXTq.

llvm-svn: 89693

ARMInstrFormats.td and fixing VLD[234]LN* and VST[234]LN* to derive from NLdSt
instead of NLdStLN.

llvm-svn: 89684

should be left unspecified now that Bob Wilson has fixed pr5470.

llvm-svn: 89676

llvm-svn: 89672

llvm-svn: 89618

llvm-svn: 89576

isn't necessary.

llvm-svn: 89568

backtraces.

llvm-svn: 89562

Add predicate operand to NEON instructions. Fix lots (but not all) 80 col violations in ARMInstrNEON.td.

llvm-svn: 89542