Commits · d971a1123f744c8d56de832260fa19ab9d5d0116 · Roger Ferrer / llvm-epi-0.8 · GitLab

This project is archived. Its data is read-only.

Nov 01, 2016
- [AMDGPU] Check if type transforms to i16 (VI+) when getting AMDGPUISD::FFBH_U32 · d971a112
  Konstantin Zhuravlyov authored Nov 01, 2016
  d971a112
- AMDGPU: Implement expansion of f16 = FP_TO_FP16 f64 · 94c21bc0
  Tom Stellard authored Nov 01, 2016
  94c21bc0
- This is a 1 character fix for an ARM build attribute test (r284571): the · b187f5d9
  Sjoerd Meijer authored Nov 01, 2016
  b187f5d9
- [Sparc][LEON] Test for FixFDIVSQRT erratum fix. · 30de1de1
  Chris Dewhurst authored Nov 01, 2016
  30de1de1
- [Thumb-1] Synthesize TBB/TBH instructions to make use of compressed jump tables · 70a3d6df
  James Molloy authored Nov 01, 2016
  70a3d6df
- [AMDGPU] Expand vector mulhu/mulhs · 8a89d366
  Valery Pykhtin authored Nov 01, 2016
  8a89d366
- [PowerPC] Implement vector shift builtins - llvm portion · e70fa633
  Nemanja Ivanovic authored Nov 01, 2016
  e70fa633
- [DAG] disable nsw/nuw for add/sub/mul when simplifying based on demanded bits (PR30841) · 70c5f02d
  Sanjay Patel authored Oct 31, 2016
  70c5f02d
Oct 31, 2016
- CodeGen: further loosen -O0 CG for WoA division · e1aa782b
  Saleem Abdulrasool authored Oct 31, 2016
  e1aa782b
- [NVPTX] Remove NVPTXFavorNonGenericAddrSpaces pass. · ed1e312f
  Justin Lebar authored Oct 31, 2016
  ed1e312f
- [PPC] add absolute difference altivec instructions and matching intrinsics · 60bdfe5a
  Nemanja Ivanovic authored Oct 31, 2016
  60bdfe5a
- GlobalISel: allow truncating pointer casts on AArch64. · 037af52c
  Tim Northover authored Oct 31, 2016
  037af52c
- GlobalISel: translate stack protector intrinsics · cdf23f1d
  Tim Northover authored Oct 31, 2016
  cdf23f1d
- [Hexagon] Don't expand mux instructions with both sources identical · 22586dcb
  Krzysztof Parzyszek authored Oct 31, 2016
  22586dcb
- Add triple to test so it does not fail on windows. · 7c41f20a
  Manuel Klimek authored Oct 31, 2016
  7c41f20a
- Delete .s file that did not test anything, and check in test that works. · bab67d2a
  Manuel Klimek authored Oct 31, 2016
  bab67d2a
- [AVX-512] Add missing patterns for selecting masked vector extracts that started from shuffles. · d4e58070
  Craig Topper authored Oct 31, 2016
  d4e58070
Oct 30, 2016
- [DAG] x | x --> x · 339a51ac
  Sanjay Patel authored Oct 30, 2016
  339a51ac
- [DAG] x & x --> x · 13aee345
  Sanjay Patel authored Oct 30, 2016
  13aee345
- [x86] add tests for basic logic op folds · 8a5f9810
  Sanjay Patel authored Oct 30, 2016
  8a5f9810
Oct 29, 2016
- [ValueTracking] recognize more variants of smin/smax · 36eeb6d6
  Sanjay Patel authored Oct 29, 2016
  36eeb6d6
- [x86] add tests for smin/smax matchSelPattern (D26091) · e9fa95e5
  Sanjay Patel authored Oct 29, 2016
  e9fa95e5
- [DAGCombiner] (REAPPLIED) Add vector demanded elements support to computeKnownBits · 75a697a1
  Simon Pilgrim authored Oct 29, 2016
  75a697a1
- Fixed FMA + FNEG combine. · 519b4ccd
  Elena Demikhovsky authored Oct 29, 2016
  519b4ccd
- AMDGPU: Use 1/2pi inline imm on VI · c88ba36e
  Matt Arsenault authored Oct 29, 2016
  c88ba36e
- [DAGCombiner] Fix a crash visiting `AND` nodes. · 86168b23
  Davide Italiano authored Oct 28, 2016
  86168b23
- AMDGPU/SI: Don't use non-0 waitcnt values when waiting on Flat instructions · 6695ba04
  Tom Stellard authored Oct 28, 2016
  6695ba04
Oct 28, 2016
- AMDGPU: Add definitions for scalar store instructions · 7b647556
  Matt Arsenault authored Oct 28, 2016
  7b647556
- [NVPTX] Compute 'rem' using the result of 'div', if possible. · f0a80ba3
  Justin Lebar authored Oct 28, 2016
  f0a80ba3
- AMDGPU: Change check prefix in test · b5f2bb1a
  Matt Arsenault authored Oct 28, 2016
  b5f2bb1a
- AMDGPU: Diagnose using too many SGPRs · 4eae3019
  Matt Arsenault authored Oct 28, 2016
  4eae3019
- Handle non-~0 lane masks on live-in registers in LivePhysRegs · 2717175c
  Krzysztof Parzyszek authored Oct 28, 2016
  2717175c
- AMDGPU: Fix using incorrect private resource with no allocation · 08906a3c
  Matt Arsenault authored Oct 28, 2016
  08906a3c
- Implement vector count leading/trailing bytes with zero lsb and vector parity · e28a0fc7
  Nemanja Ivanovic authored Oct 28, 2016
  e28a0fc7
- Make swift calling convention test specific to armv7 · 6200b2b6
  Arnold Schwaighofer authored Oct 28, 2016
  6200b2b6
- [x86] add tests for missed umin/umax · 03a585e8
  Sanjay Patel authored Oct 28, 2016
  03a585e8
- More swift calling convention tests · 7f4b31c0
  Arnold Schwaighofer authored Oct 28, 2016
  7f4b31c0
- [Hexagon] Maintain kill flags through splitting in expand-condsets · 87a47be0
  Krzysztof Parzyszek authored Oct 28, 2016
  87a47be0
- Revert "[DAGCombiner] Add vector demanded elements support to computeKnownBits" · 5cee232b
  Juergen Ributzka authored Oct 28, 2016
  5cee232b
- AMDGPU/SI: Handle hazard with s_rfe_b64 · aea899e2
  Tom Stellard authored Oct 27, 2016
  aea899e2