multiple dies per function and support C++ basenames.

llvm-svn: 144304

Add additional checking to ensure that MachineMemOperands are never set to null, which can happen in weird circumstances where target intrinsic hooks are implemented incorrectly.

llvm-svn: 144303

More of rdar://9704684

llvm-svn: 144301

llvm-svn: 144300

require this tool to resolve (currently).

llvm-svn: 144299

llvm-svn: 144298

Start of rdar://9704684

llvm-svn: 144293

consistency with other targets.

llvm-svn: 144292

llvm-svn: 144291

test/CodeGen/X86/lsr-loop-exit-cond.ll: Try to appease linux and freebsd bots to specify explicit -mtriple=x86_64-darwin.

I guess it expects -relocation-model=pic.

llvm-svn: 144290

instruction lower optimization" in the pre-RA scheduler.

The optimization, rather the hack, was done before MI use-list was available.
Now we should be able to implement it in a better way, perhaps in the
two-address pass until a MI scheduler is available.

Now that the scheduler has to backtrack to handle call sequences. Adding
artificial scheduling constraints is just not safe. Furthermore, the hack
is not taking all the other scheduling decisions into consideration so it's just
as likely to pessimize code. So I view disabling this optimization goodness
regardless of PR11314.

llvm-svn: 144267

Note: These patterns only works in some cases because
many times the load sd node is bitcasted from a load
node of a different type.

llvm-svn: 144266

determine if the value is negative and flip the sign accordingly.
rdar://10422026

llvm-svn: 144258

options to llvm-build, so the all-targets etc. components are defined properly.

llvm-svn: 144255

handle defining the "magic" target related components (like native,
nativecodegen, and engine).
 - We still require these components to be in the project (currently in
   lib/Target) so that we have a place to document them and hopefully make it
   more obvious that they are "magic".

llvm-svn: 144253

llvm-svn: 144252

change the generated library .a file name once we fully switch over, but
simplifies how we treat these targets without requiring more special casing
(since their library group name and the codegen library name currently map to
the same "llvm-config" style component name).

llvm-svn: 144251

 - Gives us a place to hang target specific metadata (like whether the target has a JIT).

llvm-svn: 144250

llvm-svn: 144249

The TII.foldMemoryOperand hook preserves implicit operands from the
original instruction.  This is not what we want when those implicit
operands refer to the register being spilled.

Implicit operands referring to other registers are preserved.

This fixes PR11347.

llvm-svn: 144247

llvm-svn: 144245

llvm-svn: 144244

llvm-svn: 144243

rdar://10422955

llvm-svn: 144242

llvm-svn: 144241

Currently checks alignment and killing stores on a power of 2 boundary as this is likely
to trim the size of the earlier store without breaking large vector stores into scalar ones.

Fixes <rdar://problem/10140300>

llvm-svn: 144239

llvm-svn: 144236

llvm-svn: 144216

rdar://10418009

llvm-svn: 144213

llvm-svn: 144212

llvm-svn: 144211

llvm-svn: 144209

llvm-svn: 144204

enough to have this be useful.

llvm-svn: 144202

 - Also, fix a refacto that left extra "all" component in list (this is now
   defined in the groups explicitly)
 - Reapply of r143879 now that Make should see needed deps.

llvm-svn: 144201

llvm-svn: 144198

llvm-svn: 144197

llvm-svn: 144194

dragonegg self-host buildbot will recover (it is complaining about object
files differing between different build stages).  Original commit message:

Add a hack to the scheduler to disable pseudo-two-address dependencies in
basic blocks containing calls. This works around a problem in which
these artificial dependencies can get tied up in calling seqeunce
scheduling in a way that makes the graph unschedulable with the current
approach of using artificial physical register dependencies for calling
sequences. This fixes PR11314.

llvm-svn: 144188

llvm-svn: 144187