one use. This allows more CMOV instructions.

llvm-svn: 25634

Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.

llvm-svn: 25606

llvm-svn: 25602

llvm-svn: 25596

llvm-svn: 25584

node, fixing fastcc and the case where a function has a frame pointer due
to dynamic allocas.

llvm-svn: 25580

llvm-svn: 25484

llvm-svn: 25457

llvm-svn: 25435

llvm-svn: 25416

llvm-svn: 25415

llvm-svn: 25413

expand it), so ask legalizer to expand i32 UINT_TO_FP.

llvm-svn: 25386

llvm-svn: 25381

read a flag.

llvm-svn: 25378

llvm-svn: 25368

llvm-svn: 25333

llvm-svn: 25312

flipped around.

llvm-svn: 25290

llvm-svn: 25278

llvm-svn: 25272

llvm-svn: 25261

llvm-svn: 25260

llvm-svn: 25259

llvm-svn: 25257

linked together).

llvm-svn: 25247

  LEA32r.
* Do not lower GlobalAddress to TargetGlobalAddress. Let isel does it.

llvm-svn: 25246

llvm-svn: 25232

llvm-svn: 25226

Add dag combiner code to recognize rotl, rotr
Add ppc code to match rotl

Targets should add rotl/rotr patterns if they have them

llvm-svn: 25222

* Allow a register node as SelectAddr() base.
* ExternalSymbol -> TargetExternalSymbol as direct function callee.
* Use X86::ESP register rather than CopyFromReg(X86::ESP) as stack ptr for
  call parmater passing.

llvm-svn: 25207

llvm-svn: 25190

llvm-svn: 25188

llvm-svn: 25162

llvm-svn: 25160

llvm-svn: 25158

* FP cmp, setcc, etc.

llvm-svn: 25117

llvm-svn: 25105

inserted in the code.

llvm-svn: 25104

llvm-svn: 25103