llvm-svn: 97098

126.gcc nightly tests. These failures uncovered latent bugs that machine DCE
could remove one half of a stack adjust down/up pair, causing PEI to assert.
This update fixes that, and the tests now pass.

llvm-svn: 96822

llvm-svn: 96393

llvm-svn: 96388

llvm-svn: 95884

tMOVCCi pattern only valid for low registers, as the Thumb1 mov immediate to
register instruction only works with low registers. Allowing high registers
for the instruction resulted in the assembler choosing the wide (32-bit)
encoding for the mov, but LLVM though the instruction was only 16 bits wide,
so offset calculations for constant pools became incorrect, leading to
out of range constant pool entries.

llvm-svn: 95686

llvm-svn: 95603

llvm-svn: 94627

cannot be directly interchanged for comparisons against negated values.
Disable the CMN instructions for the time being.

llvm-svn: 94119

the various MOV (register) instructions (16-bit Thumb), including tBRIND (the
indirect branch).  Instead of '1', it should be specified as '?', because GPR
only specifies the register class, which includes both hi-and-lo registers.

llvm-svn: 93759

the disassembler can properly decode Load/Store register/immediate instructions.

llvm-svn: 93471

llvm-svn: 93349

It was only being used by instructions with the t_addrmode_sp addressing mode,
and that is pattern matched in a way that guarantees SP is used. There is
never any register allocation done from this class.

llvm-svn: 93280

Certain Thumb instructions require only SP (e.g. tSTRspi).

llvm-svn: 91944

llvm-svn: 91571

bytes of Inst to 0x0000 for the benefit of the Thumb decoder.

llvm-svn: 91496

llvm-svn: 91434

llvm-svn: 90246

llvm-svn: 89478

llvm-svn: 89328

  load of a GV from constantpool and then add pc. It allows the code sequence to
  be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
  instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
  to this pass. This is done before post regalloc scheduling to allow the
  scheduler to proper schedule these instructions. It also allow them to be
  if-converted and shrunk by later passes.

llvm-svn: 86304

llvm-svn: 86019

llvm-svn: 85980

between ARM/Thumb modes and does not require the low bit of the target
address to be set for Thumb.

llvm-svn: 85874

llvm-svn: 85824

llvm-svn: 85698

clang/test/CodeGen/indirect-goto.c runs! (unoptimized)

llvm-svn: 85577

bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.

llvm-svn: 85517

opcode and operand with a tab.  Check for these instructions in the usual
places.

llvm-svn: 85411

Change Thumb1 and Thumb2 instructions to separate opcode from operands with a tab instead of a space.

llvm-svn: 85184

ld / st pairs, etc.

llvm-svn: 83197

Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions.

llvm-svn: 83191

Patch by Sylvere Teissier.

llvm-svn: 83135

llvm-svn: 81306

llvm-svn: 80956

llvm-svn: 80615

llvm-svn: 80350

llvm-svn: 80322

several things other than Neon vector lane numbers.  For inline assembly
operands with a "c" print code, check that they really are immediates.

llvm-svn: 79676

llvm-svn: 79535