- Jun 27, 2011
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Evan Cheng authored
into XXXGenRegisterInfo.inc. llvm-svn: 133922
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Jakob Stoklund Olesen authored
This allows for more live scratch registers which is needed to handle live ST registers before return and inline asm instructions. llvm-svn: 133903
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- Jun 25, 2011
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Chad Rosier authored
llvm-svn: 133874
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Dan Bailey authored
The .b8 operations in PTX are far more limiting than I first thought. The mov operation isn't even supported, so there's no way of converting a .pred value into a .b8 without going via .b16, which is not sensible. An improved implementation needs to use the fact that loads and stores automatically extend and truncate to implement support for EXTLOAD and TRUNCSTORE in order to correctly support boolean values. llvm-svn: 133873
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Chad Rosier authored
<rdar://problem/9483883> llvm-svn: 133858
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Douglas Gregor authored
llvm-svn: 133853
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Evan Cheng authored
llvm-svn: 133847
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Evan Cheng authored
llvm-svn: 133846
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Jim Grosbach authored
Move the target-specific RecordRelocation logic out of the generic MC MachObjectWriter and into the target-specific object writers. This allows nuking quite a bit of target knowledge from the supposedly target-independent bits in lib/MC. llvm-svn: 133844
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Rafael Espindola authored
llvm-svn: 133830
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- Jun 24, 2011
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Chad Rosier authored
overheads. No functional change intended. llvm-svn: 133824
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Evan Cheng authored
- Rename TargetRegisterDesc to MCRegisterDesc. llvm-svn: 133820
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Jim Grosbach authored
The fixup value comes in as the whole 32-bit value, so for the lo16 fixup, the upper bits need to be masked off. Previously we assumed the masking had already been done and asserted. rdar://9635991 llvm-svn: 133818
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Dan Bailey authored
The i8 type is required for boolean values, but can only use ld, st and mov instructions. The i1 type continues to be used for predicates. llvm-svn: 133814
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Chad Rosier authored
instructions can be used to match combinations of multiply/divide and VCVT (between floating-point and integer, Advanced SIMD). Basically the VCVT immediate operand that specifies the number of fraction bits corresponds to a floating-point multiply or divide by the corresponding power of 2. For example, VCVT (floating-point to fixed-point, Advanced SIMD) can replace a combination of VMUL and VCVT (floating-point to integer) as follows: Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): vmul.f32 d16, d17, d16 vcvt.s32.f32 d16, d16 becomes: vcvt.s32.f32 d16, d16, #3 Similarly, VCVT (fixed-point to floating-point, Advanced SIMD) can replace a combinations of VCVT (integer to floating-point) and VDIV as follows: Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): vcvt.f32.s32 d16, d16 vdiv.f32 d16, d17, d16 becomes: vcvt.f32.s32 d16, d16, #3 llvm-svn: 133813
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Justin Holewinski authored
.file and .loc directives. Ideally, we would utilize the existing support in AsmPrinter for this, but I cannot find a way to get .file and .loc directives to print without the rest of the associated DWARF sections, which ptxas cannot handle. llvm-svn: 133812
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Akira Hatanaka authored
enables SelectionDAG::getLoad at MipsISelLowering.cpp:1914 to return a pre-existing node instead of redundantly create a new node every time it is called. llvm-svn: 133811
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Akira Hatanaka authored
static variables or functions. llvm-svn: 133803
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Justin Holewinski authored
targets: g80, gt200, gf100(fermi) llvm-svn: 133799
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Rafael Espindola authored
llvm-svn: 133792
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Evan Cheng authored
llvm-svn: 133787
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Evan Cheng authored
target machine from those that are only needed by codegen. The goal is to sink the essential target description into MC layer so we can start building MC based tools without needing to link in the entire codegen. First step is to refactor TargetRegisterInfo. This patch added a base class MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to separate register description from the rest of the stuff. llvm-svn: 133782
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- Jun 23, 2011
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Eli Friedman authored
llvm-svn: 133759
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Evan Cheng authored
llvm-svn: 133739
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Evan Cheng authored
llvm-svn: 133738
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Justin Holewinski authored
parameters if SM >= 2.0 - Update test cases to be more robust against register allocation changes - Bump up the number of registers to 128 per type - Include Python script to re-generate register file with any number of registers llvm-svn: 133736
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Justin Holewinski authored
llvm-svn: 133734
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Justin Holewinski authored
st.param and ld.param FIXME: Test cases still need to be updated llvm-svn: 133733
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Justin Holewinski authored
FIXME: DCE is eliminating the final st.param.x calls, figure out why llvm-svn: 133732
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Evan Cheng authored
llvm-svn: 133726
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Dylan Noblesmith authored
This broke after r133364. llvm-svn: 133709
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Jay Foad authored
-Wshorten-64-to-32 warning in Instructions.h. llvm-svn: 133708
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Eric Christopher authored
"Reinstate r133435 and r133449 (reverted in r133499) now that the clang self-hosted build failure has been fixed (r133512)." Due to some additional warnings. llvm-svn: 133700
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Bill Wendling authored
supports compact unwind info instead of having a separate flag indicating this. llvm-svn: 133685
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Evan Cheng authored
llvm-svn: 133679
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Bill Wendling authored
llvm-svn: 133662
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Bill Wendling authored
If the linker supports it, this will hold the CIE and FDE information in a compact format. The implementation of the compact unwinding emission is coming soon. llvm-svn: 133658
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- Jun 22, 2011
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Jim Grosbach authored
llvm-svn: 133640
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Jim Grosbach authored
Just tidy up a bit. No functional change. llvm-svn: 133638
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Justin Holewinski authored
llvm-svn: 133619
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