llvm-svn: 104711

llvm-svn: 104622

Fixes rdar://8017638

llvm-svn: 104617

Use the tablegen-produced enums.

llvm-svn: 104493

llvm-svn: 104204

doesn't have a register operand. Also, use I instead of PSI, for
consistency with mfence and lfence.

llvm-svn: 104203

shifts and null vectors. Autoupgrade these to what we'd lower them to.

Add a testcase to exercise this.

llvm-svn: 101851

i8 field when they really do not.  This fixes rdar://7840289

llvm-svn: 101629

patterns to handle the lowering.

llvm-svn: 101331

Fixes PR3440.

llvm-svn: 100736

dest.

llvm-svn: 100252

a new subtarget option for AES and check for the support.  Add "westmere"
line of processors and add AES-NI support to the core i7.

Add a couple of TODOs for information I couldn't verify.

llvm-svn: 100231

aes instead of sse4.2.  Add a brief todo for a subtarget flag and rework
the aeskeygenassist instruction to more closely match the docs.

llvm-svn: 100078

llvm-svn: 99975

Since it is just a pxor in disguise, we should probably expand it to a full
polymorphic triple.

llvm-svn: 99953

Rewrite the pmulld patterns, and make sure that they fold in loads of
arguments into the instruction.

llvm-svn: 99910

the SDNodes.

llvm-svn: 99835

llvm-svn: 99770

matchable: it seems like it would always constant fold.

llvm-svn: 99758

nodes all have an EFLAGS result when made by isel lowering.

llvm-svn: 99736

llvm-svn: 99540

opcode values fitting in one byte (svn r99494).

llvm-svn: 99514

--- Reverse-merging r99440 into '.':
U    test/MC/AsmParser/X86/x86_32-bit_cat.s
U    test/MC/AsmParser/X86/x86_32-encoding.s
U    include/llvm/IntrinsicsX86.td
U    include/llvm/CodeGen/SelectionDAGNodes.h
U    lib/Target/X86/X86InstrSSE.td
U    lib/Target/X86/X86ISelLowering.h

llvm-svn: 99450

llvm-svn: 99440

override prefix and only the r/m16 forms should have had that.  Also for variant
one, the AT&T syntax, added suffixes to all forms.  Also added the missing
64-bit form for 'CRC32 r64, r/m8'.  Plus added test cases for all forms and
tweaked one test case to add the needed suffixes.

llvm-svn: 98980

to input patterns, we can fix X86ISD::CMP and X86ISD::BT as taking
two inputs (which have to be the same type) and *returning an i32*.
This is how the SDNodes get made in the graph, but we weren't able
to model it this way due to deficiencies in the pattern language.

Now we can change things like this:

 def UCOM_FpIr80: FpI_<(outs), (ins RFP80:$lhs, RFP80:$rhs), CompareFP,
-                  [(X86cmp RFP80:$lhs, RFP80:$rhs),
-                   (implicit EFLAGS)]>; // CC = ST(0) cmp ST(i)
+                  [(set EFLAGS, (X86cmp RFP80:$lhs, RFP80:$rhs))]>;

and fix terrible crimes like this:

-def : Pat<(parallel (X86cmp GR8:$src1, 0), (implicit EFLAGS)),
+def : Pat<(X86cmp GR8:$src1, 0),
           (TEST8rr GR8:$src1, GR8:$src1)>;

This relies on matching the result of TEST8rr (which is EFLAGS, which is
an implicit def) to the result of X86cmp, an i32.

llvm-svn: 98903

llvm-svn: 98531

pattern which is broken (source and address swapped).

llvm-svn: 97958

could never have matched because the operand list was backwards.

llvm-svn: 97933

Extracting the low element of a vector is now done with EXTRACT_SUBREG,
and the zero-extension performed by load movss is now modeled with
SUBREG_TO_REG, and so on.

Register-to-register movss and movsd are no longer considered copies;
they are two-address instructions which insert a scalar into a vector.

llvm-svn: 97354

llvm-svn: 97348

llvm-svn: 97201

though some look dubious afaict, these are all ok.

llvm-svn: 96899

llvm-svn: 96574

Add support for emitting non-temporal stores for DAGs marked
non-temporal.  Fix from r96241 for botched encoding of MOVNTDQ.

Add documentation for !nontemporal metadata.

Add a simpler movnt testcase.

llvm-svn: 96386

and the testcase needs improvement.

llvm-svn: 96265

Add support for emitting non-temporal stores for DAGs marked
non-temporal.

llvm-svn: 96241

encoder and decoder by using new MRM_ forms.

llvm-svn: 96048

movq	(%ecx,%edx,2), %xmm2
movhps	(%ecx,%eax,2), %xmm2

rather than:

movq     (%eax, %edx, 2), %xmm2		
movq     (%eax, %ebx, 2), %xmm3		
movlhps  %xmm3, %xmm2			

Testcase forthcoming.

llvm-svn: 95948

prefix which is part of the opcode encoding.

llvm-svn: 95729