Commits · da4a7c01bfdeb9b8647d38c57f96a9dea64dc66a · Roger Ferrer / llvm-epi-0.8 · GitLab

This project is archived. Its data is read-only.

Mar 12, 2018
- [AMDGPU][MC] Corrected GATHER4 opcodes · da4a7c01
  Dmitry Preobrazhensky authored Mar 12, 2018
  da4a7c01
Mar 06, 2018
- [ARM]Decoding MSR with unpredictable destination register causes an assert · 75c6bfea
  Simi Pallipurath authored Mar 06, 2018
  75c6bfea
Feb 23, 2018
- [PowerPC] Code cleanup. Remove instructions that were withdrawn from Power 9. · 15e6b10e
  Stefan Pintilie authored Feb 23, 2018
  15e6b10e
Feb 21, 2018
- [AMDGPU][MC] Added lds support for MUBUF instructions · d6e1a940
  Dmitry Preobrazhensky authored Feb 21, 2018
  d6e1a940
Feb 17, 2018
- [X86][3DNow!] Add PFRCP reg-reg disassembler test case (PR21168) · dbcbaee7
  Simon Pilgrim authored Feb 17, 2018
  dbcbaee7
Feb 15, 2018
- [X86][3DNOW] Teach decoder about AMD 3DNow! instrs · de9ad4ba
  Rafael Auler authored Feb 15, 2018
  de9ad4ba
Feb 14, 2018
- [X86] Don't swap argument on BOUND instruction in at&t syntax. · 67575216
  Craig Topper authored Feb 14, 2018
  67575216
Feb 08, 2018
- [ARM] Re-commit r324600 with fixed LLVMBuild.txt · 133b6085
  Oliver Stannard authored Feb 08, 2018
  133b6085
- Revert r324600 as it breaks a buildbot · 3c11ecbb
  Oliver Stannard authored Feb 08, 2018
  3c11ecbb
- [ARM] Fix disassembly of invalid banked register moves · db982b25
  Oliver Stannard authored Feb 08, 2018
  db982b25
- [mips] Define certain instructions in microMIPS32r3 · b3e7ed3b
  Stefan Maksimovic authored Feb 08, 2018
  b3e7ed3b
Feb 06, 2018
- [AArch64] Fix spelling of ICH_ELRSR_EL2 system register · 6df8f43c
  Oliver Stannard authored Feb 06, 2018
  6df8f43c
- [ARM][AArch64] Add CSDB speculation barrier instruction · ee0ac393
  Oliver Stannard authored Feb 06, 2018
  ee0ac393
Feb 05, 2018
- [AMDGPU][MC] Corrected dst/data size for MIMG opcodes with d16 modifier · 0a1ff464
  Dmitry Preobrazhensky authored Feb 05, 2018
  0a1ff464
Feb 01, 2018
- [ARM] Add support for unpredictable MVN instructions. · 490e9e67
  Yvan Roux authored Feb 01, 2018
  490e9e67
Jan 30, 2018
- AMDGPU/SI: Add decoding in the GFX80_UNPACKED decoding namespace. · 0905870f
  Changpeng Fang authored Jan 30, 2018
  0905870f
Jan 29, 2018
- [AMDGPU][MC] Corrected parsing of image opcode modifiers r128 and d16 · 4f321aef
  Dmitry Preobrazhensky authored Jan 29, 2018
  4f321aef
Jan 26, 2018
- [AMDGPU][MC] Added support of 64-bit image atomics · 0b4eb1ea
  Dmitry Preobrazhensky authored Jan 26, 2018
  0b4eb1ea
- [AMDGPU][MC] Enabled disassembler for image atomic operations · 6cb42e76
  Dmitry Preobrazhensky authored Jan 26, 2018
  6cb42e76
Jan 23, 2018
- [mips] Properly select abs and sqrt instructions · 98749e02
  Stefan Maksimovic authored Jan 23, 2018
  98749e02
Jan 17, 2018
- [AMDGPU][MC][GFX9] Enable inline constants for SDWA operands · 6b65f7c3
  Dmitry Preobrazhensky authored Jan 17, 2018
  6b65f7c3
Jan 12, 2018
- [X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics. · b1623321
  Craig Topper authored Jan 12, 2018
  b1623321
Jan 10, 2018
- [AMDGPU][MC][GFX8][GFX9] Added XNACK_MASK support · 3afbd825
  Dmitry Preobrazhensky authored Jan 10, 2018
  3afbd825
Jan 05, 2018
- [X86] Stop printing moves between VR64 and GR64 with 'movd' mnemonic. Use 'movq' instead. · 00486731
  Craig Topper authored Jan 05, 2018
  00486731
Dec 29, 2017
- [AMDGPU][MC] Incorrect parsing of flat/global atomic modifiers · 414e0538
  Dmitry Preobrazhensky authored Dec 29, 2017
  414e0538
Dec 22, 2017
- [AMDGPU][MC] Corrected parsing of optional operands for ds_swizzle_b32 · c5b0c172
  Dmitry Preobrazhensky authored Dec 22, 2017
  c5b0c172
- [AMDGPU][MC] Added support of 256- and 512-bit tuples of ttmp registers · 27134953
  Dmitry Preobrazhensky authored Dec 22, 2017
  27134953
- [X86] Add prefetchwt1 instruction and overhaul priorities and isel enabling... · e268598d
  Craig Topper authored Dec 22, 2017
  e268598d
Dec 21, 2017
- [ARM] Armv8-R DFB instruction · 98727bc2
  Sam Parker authored Dec 21, 2017
  98727bc2
Dec 20, 2017
- [AArch64] CCSIDR2 system register · daed9de6
  Sam Parker authored Dec 20, 2017
  daed9de6
Dec 13, 2017
- AMDGPU: Partially fix disassembly of MIMG instructions · cad7fa85
  Matt Arsenault authored Dec 13, 2017
  cad7fa85
Dec 11, 2017
- [AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tma · ac2b0264
  Dmitry Preobrazhensky authored Dec 11, 2017
  ac2b0264
- [mips] Removal of microMIPS64R6 · d6dada17
  Aleksandar Beserminji authored Dec 11, 2017
  d6dada17
Dec 10, 2017
- PowerPC: support external pid instructions in MC layer. · cf4701bb
  Tim Northover authored Dec 10, 2017
  cf4701bb
Dec 08, 2017
- AMDGPU/GCN: Bring processors in sync with AMDGPUUsage · c40d9f2e
  Konstantin Zhuravlyov authored Dec 08, 2017
  c40d9f2e
Dec 02, 2017
- [ARC] Add instruction subset for the ARC backend. · f665f6a2
  Tatyana Krasnukha authored Dec 02, 2017
  f665f6a2
Nov 27, 2017
- [AMDGPU][MC][DISASSEMBLER][GFX9] Corrected decoding of GLOBAL/SCRATCH opcodes · 16608e67
  Dmitry Preobrazhensky authored Nov 27, 2017
  16608e67
Nov 24, 2017
- [AMDGPU][MC][GFX9] Added v_interp_p2_f16 and v_interp_p2_legacy_f16 · 0e8924a5
  Dmitry Preobrazhensky authored Nov 24, 2017
  0e8924a5
Nov 22, 2017
- [Hexagon] Remove trailing spaces, NFC · 6acecc96
  Krzysztof Parzyszek authored Nov 22, 2017
  6acecc96
- [AMDGPU][mc][tests] Updated generated lit tests for GFX8/9 · c492500e
  Dmitry Preobrazhensky authored Nov 22, 2017
  c492500e