llvm-svn: 97529

new helper function.

llvm-svn: 97525

(the most general) the others are dead.

llvm-svn: 97511

Don't accidentally produce unspillable intervals for deeply nested loops.

llvm-svn: 97496

OPC_SwitchOpcode to use a table lookup instead of having to go
through the interpreter for this.

llvm-svn: 97469

by Micah Villmow for PR6335.

llvm-svn: 97461

llvm-svn: 97441

ComplexPattern at the root be generated multiple times, once
for each opcode they are part of.  This encourages factoring
because the opcode checks get treated just like everything
else in the matcher.

llvm-svn: 97439

to a scope where every child starts with a CheckOpcode, but
executes more efficiently.  Enhance DAGISelMatcherOpt to 
form it.

This also fixes a bug in CheckOpcode: apparently the SDNodeInfo
objects are not pointer comparable, we have to compare the
enum name.

llvm-svn: 97438

llvm-svn: 97426

(which gets #included into the middle of each 
target's DAGISel class) into a .cpp file where it is
only compiled once.

llvm-svn: 97425

case of MorphNodeTo directly.

llvm-svn: 97417

llvm-svn: 97408

llvm-svn: 97360

after LSR, so that clients can opt in.

llvm-svn: 97357

defs or uses. The regular def and use checking below covers them, and
can be more precise. It's safe to hoist an instruction with a dead
implicit def if the register isn't live into the loop header.

llvm-svn: 97352

llvm-svn: 97310

llvm-svn: 97295

for alignment into the LSDA. If the TType base offset is emitted, then put the
padding there. Otherwise, put it in the call site table length. There will be no
conflict between the two sites when placing the padding in one place.

llvm-svn: 97277

llvm-svn: 97269

The PowerPC floating point registers can represent both f32 and f64 via the
two register classes F4RC and F8RC. F8RC is considered a subclass of F4RC to
allow cross-class coalescing. This coalescing only affects whether registers
are spilled as f32 or f64.

Spill slots must be accessed with load/store instructions corresponding to the
class of the spilled register. PPCInstrInfo::foldMemoryOperandImpl was looking
at the instruction opcode which is wrong.

X86 has similar floating point register classes, but doesn't try to fold
memory operands, so there is no problem there.

llvm-svn: 97262

llvm-svn: 97261

as X86 is currently the only FastISel target.  Per review.

llvm-svn: 97255

llvm-svn: 97235

llvm-svn: 97200

the alignment requirement, if it no longer makes the TType base offset overflow
into extra bytes, then we need to pad to those bytes ourselves.

llvm-svn: 97196

llvm-svn: 97193

llvm-svn: 97192

will eliminate the need for padding in the "Call site table length". E.g., if
we have this:

    GCC_except_table1:
    Lexception1:
        .byte   0xff  ## @LPStart Encoding = omit
        .byte   0x9b  ## @TType Encoding = indirect pcrel sdata4
        .byte   0x7f  ## @TType base offset
        .byte   0x03  ## Call site Encoding = udata4
        .byte   0x89  ## Call site table length

with padding of 1. We want to emit the padding like this:
 
    GCC_except_table1:
    Lexception1:
        .byte   0xff  ## @LPStart Encoding = omit
        .byte   0x9b  ## @TType Encoding = indirect pcrel sdata4
        .byte   0xff  ## @TType base offset
        .space  1,0   ## Padding
        .byte   0x03  ## Call site Encoding = udata4
        .byte   0x89  ## Call site table length

and not with padding on the "Call site table length" entry.

llvm-svn: 97183

llvm-svn: 97169

operands are themselves vectors. Based on a patch by
Micah Villmow for PR6338.

llvm-svn: 97165

terms of store and load, which means bitcasting between scalar
integer and vector has endian-specific results, which undermines
this whole approach.

llvm-svn: 97137

llvm-svn: 97087

GCC_except_table label but before the Lexception, which the FDE references.
This causes problems as the FDE does not point to the start of an LSDA chunk.

Use an unnormalized uleb128 for the call-site table length that includes the
padding.

llvm-svn: 97078

llvm-svn: 97072

the number of value bits, not the number of bits of allocation for in-memory
storage.

Make getTypeStoreSize and getTypeAllocSize work consistently for arrays and
vectors.

Fix several places in CodeGen which compute offsets into in-memory vectors
to use TargetData information.

This fixes PR1784.

llvm-svn: 97064

more elegant.

llvm-svn: 97059

llvm-svn: 97057

Use a SmallPtrSet as suggested by Chris.

llvm-svn: 97056

the hopes of fixing PPC bootstrap.

llvm-svn: 97040