working.  The instruction selector changes will hopefully be coming later
this week once they are debugged.  This is necessary to support the darwin
x86 FP model, and is recommended by intel as the replacement for x87.  As
a bonus, the register allocator knows how to deal with these registers
across basic blocks, unliky the FP stackifier.  This leads to significantly
better codegen in several cases.

llvm-svn: 22300

currently use: llc t.bc --filetype=obj

This will produce a t.o file which is dumpable with readelf.  Currently
the file produced is empty, but the scaffolding to do more is now in place.

llvm-svn: 22292

interface.

llvm-svn: 22282

See last commit for LangRef, this implements it on all targets.

llvm-svn: 22273

llvm-svn: 22270

llvm-svn: 22254

llvm-svn: 22245

llvm-svn: 22200

llvm-svn: 22190

so that the shiny new use of std::cerr is defined.

llvm-svn: 22156

* Change assert() to std::cerr printout, as it will not appear in opt builds
* Add comments to clarify what #ifdef/#else/#endif match what condition(s)

llvm-svn: 22154

llvm-svn: 22151

llvm-svn: 22150

llvm-svn: 22147

llvm-svn: 22143

llvm-svn: 22137

doesn't know who 'called' it.

llvm-svn: 22136

llvm-svn: 22050

        add %ESP, 20
        jmp %EDX  # TAIL CALL

instead of:
        add %ESP, -8
        add %ESP, 28
        jmp %EDX  # TAIL CALL

llvm-svn: 22047

tail calls.

llvm-svn: 22046

sorta-pseudo-instruction

llvm-svn: 22042

llvm-svn: 22040

adjustment.  If so, we merge the adjustment into the existing one.  This
allows us to generate:

caller2:
        sub %ESP, 12
        mov DWORD PTR [%ESP], 0
        mov %EAX, 1234567890
        mov %EDX, 0
        call func2
        add %ESP, 8
        ret 4

intead of:

caller2:
        sub %ESP, 12
        mov DWORD PTR [%ESP], 0
        mov %EAX, 1234567890
        mov %EDX, 0
        call func2
        sub %ESP, 4
        add %ESP, 12
        ret 4

for X86/fast-cc-merge-stack-adj.ll

llvm-svn: 22038

llvm-svn: 22036

This fixes fourinarow with -enable-x86-fastcc.

llvm-svn: 22022

to do ugly hackery to avoid emitting code like this:

   call foo
   mov vreg, EAX
   adjcallstackup ...

If foo is a fastcc call and if vreg gets spilled, we might end up with this:

   call foo
   mov [ESP+offset], EAX     ;; Offset doesn't consider the 12!
   sub ESP, 12

Which is bad.  The previous hacky code to deal with this was A) gross B) not
good enough.  In particular, it could miss cases and emit the bad code above.
Now we always emit this:

   call foo
   adjcallstackup ...
   mov vreg, EAX

directly.

This makes fastcc with callees poping the stack work much better.  Next
stop (finally!) really is tail calls.

llvm-svn: 22021

This should fix some missing symbols problems on BSD and improve performance
of programs that use that operation.

llvm-svn: 22012

is always 8-byte aligned for fastcc

llvm-svn: 21995

llvm-svn: 21991

llvm-svn: 21988

llvm-svn: 21986

llvm-svn: 21985

do not use

llvm-svn: 21984

llvm-svn: 21980

llvm-svn: 21976

llvm-svn: 21958

llvm-svn: 21945

each live in, and copy the regs from the vregs.  As the very first thing we
do in the function, insert copies from the pregs to the vregs.  This fixes
problems where the token chain of CopyFromReg was not enough to allow reordering
of the copyfromreg nodes and other unchained nodes (e.g. div, which clobbers
eax on intel).

llvm-svn: 21932

llvm-svn: 21915

two integer values in registers for the fastcc calling conv.

llvm-svn: 21912