llvm-svn: 70466

llvm-svn: 70461

which better identifies what the optimization is doing. And is more flexible for
future uses.

llvm-svn: 70440

llvm-svn: 70425

llvm-svn: 70372

Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to
use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.

Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'll change the JIT with a follow-up patch.

llvm-svn: 70343

This should fix PR3379 and PR4064.
Patch inspired by Edwin Török!

llvm-svn: 70328

llvm-svn: 70275

use the old behavior, the flag is -O0. This change allows for finer-grained
control over which optimizations are run at different -O levels.

Most of this work was pretty mechanical. The majority of the fixes came from
verifying that a "fast" variable wasn't used anymore. The JIT still uses a
"Fast" flag. I'm not 100% sure if it's necessary to change it there...

llvm-svn: 70270

PR2957

ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask.  A value of -1 represents UNDEF.

In addition to eliminating the creation of illegal BUILD_VECTORS just to 
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.

llvm-svn: 70225

to precisely describe the h-register subreg register classes.
Thanks to Jakob Stoklund Olesen for spotting this and for the
initial patch!

Also, make getStoreRegOpcode and getLoadRegOpcode aware of the
needs of h registers.

llvm-svn: 70211

GR32_ABCD, and GR64_ABCD, respectively, to help describe them.

llvm-svn: 70210

llvm-svn: 70209

llvm-svn: 70197

Nicolas Capens!

llvm-svn: 70057

very elegant, but neither is the tls specification :-(

llvm-svn: 69968

llvm-svn: 69967

ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask.  A value of -1 represents UNDEF.

In addition to eliminating the creation of illegal BUILD_VECTORS just to 
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.

A clean up of x86 shuffle code, and some canonicalizing in DAGCombiner is next.

llvm-svn: 69952

memory operand tuples. This doesn't ever come up in normal
code however.

llvm-svn: 69848

Spotted by gcc-4.5.

llvm-svn: 69673

This fixes PR4002.

llvm-svn: 69672

This makes the extra copyRegToReg calls in ScheduleDAGSDNodesEmit.cpp
unnecessary. Derived from a patch by Jakob Stoklund Olesen.

llvm-svn: 69635

in the MachineFunction class, renaming it to addLiveIn for consistency with
the same method in MachineBasicBlock.  Thanks for Anton for suggesting this.

llvm-svn: 69615

llvm-svn: 69417

llvm-svn: 69394

leaq	foo@TLSGD(%rip), %rdi

as part of the instruction sequence. Using a register other than %rdi and then
copying it to %rdi is not valid.

llvm-svn: 69350

llvm-svn: 69347

matter, because this instruction isn't generated until after
things that care.

llvm-svn: 69336

present, but it's inconsistent.

llvm-svn: 69335

llvm-svn: 69284

llvm-svn: 69204

llvm-svn: 69203

llvm-svn: 69127

the local register allocator.

llvm-svn: 69115

either the source or destination is a physical h register.

This fixes sqlite3 with the post-RA scheduler enabled.

llvm-svn: 69111

REX prefixes.

llvm-svn: 69108

any non-address uses of the address value. This fixes 186.crafty.

llvm-svn: 69094

llvm-svn: 69049

it accordingly. Thanks to Jakob Stoklund Olesen for pointing
out how this might be useful.

llvm-svn: 68986

Reapply 68847.
Now debug_inlined section is covered by TAI->doesDwarfUsesInlineInfoSection(), which is false by default.

llvm-svn: 68964