Commits · db78273b6ea5cdce18c768fce5a1bdf55d61d91d · Roger Ferrer / llvm-epi-0.8 · GitLab

This project is archived. Its data is read-only.

Jul 20, 2017
- Add an ID field to StackObjects · db78273b
  Matt Arsenault authored Jul 20, 2017
  db78273b
Jul 18, 2017
- AMDGPU: Fix crash when folding immediates into multiple uses · a253e4c0
  Nicolai Haehnle authored Jul 18, 2017
  a253e4c0
Jul 14, 2017
- [AArch64][Falkor] Avoid HW prefetcher tag collisions (step 1) · b1e8714a
  Geoff Berry authored Jul 14, 2017
  b1e8714a
Jul 13, 2017
- [MIR] Add support for printing and parsing target MMO flags · 6748abe2
  Geoff Berry authored Jul 13, 2017
  6748abe2
Jul 12, 2017
- Enhance synchscope representation · bb80d3e1
  Konstantin Zhuravlyov authored Jul 11, 2017
  bb80d3e1
Jul 10, 2017
- AMDGPU: Allow SIShrinkInstructions to work in non-SSA · 6c29c5ac
  Matt Arsenault authored Jul 10, 2017
  6c29c5ac
- [Hexagon] Handle Hexagon-specific machine operand target flags in MIR · 0ac065f3
  Krzysztof Parzyszek authored Jul 10, 2017
  0ac065f3
Jul 07, 2017
- [RegAllocFast] Add the proper initialize method to use the .mir infrastructure · 81551148
  Quentin Colombet authored Jul 07, 2017
  81551148
Jul 06, 2017
- [MachineVerifier] Add check that tied physregs aren't different. · 9c3e2eac
  Mikael Holmen authored Jul 06, 2017
  9c3e2eac
Jul 03, 2017
- AMDGPU: Add operand target flags serialization · 3f031e75
  Matt Arsenault authored Jul 02, 2017
  3f031e75
Jun 30, 2017
- Remove redundant copy in recurrences · 0e35ea3b
  Taewook Oh authored Jun 29, 2017
  0e35ea3b
Jun 06, 2017
- llc: Add ability to parse mir from stdin · 7e23fc05
  Matthias Braun authored Jun 06, 2017
  7e23fc05
- MIRPrinter: Avoid assert() when printing empty INLINEASM strings. · 8b5f9e44
  Matthias Braun authored Jun 06, 2017
  8b5f9e44
- · 56d87ef5
  Vivek Pandya authored Jun 06, 2017
  56d87ef5
- CodeGen: Refactor MIR parsing · 7bda1958
  Matthias Braun authored Jun 06, 2017
  7bda1958
Jun 03, 2017
- [RABasic] Properly initialize the pass · ebbaed6d
  Quentin Colombet authored Jun 02, 2017
  ebbaed6d
May 31, 2017
- TargetMachine: Indicate whether machine verifier passes. · d6a36ae2
  Matthias Braun authored May 31, 2017
  d6a36ae2
May 29, 2017
- Revert "[IfConversion] Keep the CFG updated incrementally in IfConvertTriangle" · 8cf785f6
  Tobias Grosser authored May 29, 2017
  8cf785f6
May 24, 2017
- Move machine-cse-physreg.mir to test/CodeGen/Thumb · 6a0005d1
  Krzysztof Parzyszek authored May 24, 2017
  6a0005d1
- MachineCSE: Respect interblock physreg liveness · 2676f826
  Mikael Holmen authored May 24, 2017
  2676f826
May 12, 2017
- [IfConversion] Keep the CFG updated incrementally in IfConvertTriangle · ce3ec451
  Mikael Holmen authored May 12, 2017
  ce3ec451
May 10, 2017
- [IfConversion] Add missing check in IfConversion/canFallThroughTo · 21c867c2
  Mikael Holmen authored May 10, 2017
  21c867c2
May 09, 2017
- Add extra operand to CALLSEQ_START to keep frame part set up previously · d526b13e
  Serge Pavlov authored May 09, 2017
  d526b13e
May 05, 2017
- Add missing target triple to test · c1c56916
  Matthias Braun authored May 05, 2017
  c1c56916
- MIParser/MIRPrinter: Compute block successors if not explicitely specified · 8940114f
  Matthias Braun authored May 05, 2017
  8940114f
May 02, 2017
- MachineFrameInfo: Track whether MaxCallFrameSize is computed yet; NFC · ab9438cb
  Matthias Braun authored May 01, 2017
  ab9438cb
Apr 11, 2017
- MIR: Allow parsing of empty machine functions · 20dd36a4
  Justin Bogner authored Apr 11, 2017
  20dd36a4
Apr 03, 2017
- AMDGPU: Remove legacy bfe intrinsics · 754dd3ea
  Matt Arsenault authored Apr 03, 2017
  754dd3ea
Mar 21, 2017
- AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel · 3dbeefa9
  Matt Arsenault authored Mar 21, 2017
  3dbeefa9
Mar 19, 2017
- [MIR] Test assumes x64 windows calling convention upon printing/parsing MIR output/input. · 75537b65
  Oren Ben Simhon authored Mar 19, 2017
  75537b65
- [MIR] Add triple to test that assumes it runs on windows. · 6520f83b
  Benjamin Kramer authored Mar 19, 2017
  6520f83b
- Moving the test to x86 because other architectures do not suport regcall calling convention. · a96fdbf2
  Oren Ben Simhon authored Mar 19, 2017
  a96fdbf2
- [MIR] Support Customed Register Mask and CSRs · 0ef61ec3
  Oren Ben Simhon authored Mar 19, 2017
  0ef61ec3
Feb 22, 2017
- MIRTests: Remove unnecessary 2>&1 redirection · f1141285
  Matthias Braun authored Feb 22, 2017
  f1141285
Feb 21, 2017
- AMDGPU: Remove dead declarations from MIR tests · b2e6811e
  Matt Arsenault authored Feb 21, 2017
  b2e6811e
Feb 13, 2017
- MIR: parse & print the atomic parts of a MachineMemOperand. · b73e3090
  Tim Northover authored Feb 13, 2017
  b73e3090
Jan 20, 2017
- [MIRParser] Allow generic register specification on operand. · bf480554
  Ahmed Bougacha authored Jan 20, 2017
  bf480554
Jan 18, 2017
- MIRParser: Allow regclass specification on operand · de5fea2c
  Matthias Braun authored Jan 18, 2017
  de5fea2c
Jan 05, 2017
- [AArch64] Fold some filled/spilled subreg COPYs · d46b6e80
  Geoff Berry authored Jan 05, 2017
  d46b6e80
- CodeGen: Assert that liveness is up to date when reading block live-ins. · 11723322
  Matthias Braun authored Jan 05, 2017
  11723322