llvm-svn: 33960

foldMemoryOperand() cannot fold tMOVrr sp into load / store in thumb mode. tLDRspi / tSTRspi cannot target / store high registers.

llvm-svn: 33958

llvm-svn: 33945

- If c does not fit in the offset field, materialize sp + c into a register
  using tADDhirr.

llvm-svn: 33944

must in order for backends that do want to support large integer types to be
able to function. Consequently, don't assert if the bitwidth > 64 bits
when computing the size and alignment. Instead, compute the size by rounding
up to the next even number of bytes for the size. Compute the alignment
as the same as the LongABIAlignment. These provide reasonable defaults
that the target can override.

llvm-svn: 33943

This patch replaces the SymbolTable class with ValueSymbolTable which does
not support types planes. This means that all symbol names in LLVM must now
be unique. The patch addresses the necessary changes to deal with this and
removes code no longer needed as a result. This completes the bulk of the
changes for this PR. Some cleanup patches will follow.

llvm-svn: 33918

X + C to promote LEA formation.  We would incorrectly apply it in some cases
(test) and miss it in others.

This fixes CodeGen/X86/2007-02-04-OrAddrMode.ll

llvm-svn: 33884

llvm-svn: 33832

llvm-svn: 33831

non-Mach-O-specific information.

llvm-svn: 33819

PPCMachOWriter is now trivial.

llvm-svn: 33818

llvm-svn: 33817

- Add debugging info.

llvm-svn: 33811

llvm-svn: 33800

llvm-svn: 33795

llvm-svn: 33789

llvm-svn: 33788

llvm-svn: 33780

llvm-svn: 33778

This feature is needed in order to support shifts of more than 255 bits
on large integer types.  This changes the syntax for llvm assembly to
make shl, ashr and lshr instructions look like a binary operator:
   shl i32 %X, 1
instead of
   shl i32 %X, i8 1
Additionally, this should help a few passes perform additional optimizations.

llvm-svn: 33776

llvm-svn: 33775

llvm-svn: 33773

llvm-svn: 33763

llvm-svn: 33762

llvm-svn: 33759

llvm-svn: 33755

- In thumb mode, a new constpool island BB size should be 4 + 2 to
  compensate for the potential padding due to alignment requirement.

llvm-svn: 33753

affected part is codegen of "memove" inside x86 backend. This fixes
PR1144

llvm-svn: 33752

to just before the add r1, pc:

Before:
        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
LPCRELL0:
        mov r1, #PCRELV0
        add r1, pc

Now:
        .set PCRELV0, (LJTI1_0_0-(LPCRELL0+4))
        mov r1, #PCRELV0
LPCRELL0:
        add r1, pc

llvm-svn: 33744

llvm-svn: 33743

llvm-svn: 33741

there follows a sp increment for the va register save region. Instead issue
a separate pop to another register, increment sp, and then return:
        pop {r4, r5, r6, r7}
        pop {r3}
        add sp, #3 * 4
        bx r3

llvm-svn: 33739

two bytes padding.

llvm-svn: 33734

llvm-svn: 33733

llvm-svn: 33732

llvm-svn: 33729

instructions away, i.e. its address is equal to PC.
        %r0 = tLDRpci <cp#0>
        bx
        CONSTPOOL_ENTRY 0 <cp#0>, 4

llvm-svn: 33728

llvm-svn: 33727

llvm-svn: 33724

llvm-svn: 33723